mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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d4e6f98d7f
1. Add PMIC shutdown API 2. Add PMIC low power settings Change-Id: I634a60fa3e2a74a6031df9fe59e2f52956ef7114 Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
2200 lines
115 KiB
C
2200 lines
115 KiB
C
/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT6373_LOWPOWER_REG_H
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#define MT6373_LOWPOWER_REG_H
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#define MT6373_RG_BUCK_VBUCK0_VOSEL_SLEEP_ADDR 0x1487
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#define MT6373_RG_BUCK_VBUCK0_ONLV_EN_ADDR 0x1488
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#define MT6373_RG_BUCK_VBUCK0_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK0_RC0_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC1_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC2_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC3_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC4_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC5_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC6_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC7_OP_EN_ADDR 0x148D
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#define MT6373_RG_BUCK_VBUCK0_RC8_OP_EN_ADDR 0x148E
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#define MT6373_RG_BUCK_VBUCK0_RC9_OP_EN_ADDR 0x148E
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#define MT6373_RG_BUCK_VBUCK0_RC10_OP_EN_ADDR 0x148E
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#define MT6373_RG_BUCK_VBUCK0_RC11_OP_EN_ADDR 0x148E
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#define MT6373_RG_BUCK_VBUCK0_RC12_OP_EN_ADDR 0x148E
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#define MT6373_RG_BUCK_VBUCK0_RC13_OP_EN_ADDR 0x148E
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#define MT6373_RG_BUCK_VBUCK0_HW0_OP_EN_ADDR 0x148F
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#define MT6373_RG_BUCK_VBUCK0_HW1_OP_EN_ADDR 0x148F
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#define MT6373_RG_BUCK_VBUCK0_HW2_OP_EN_ADDR 0x148F
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#define MT6373_RG_BUCK_VBUCK0_HW3_OP_EN_ADDR 0x148F
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#define MT6373_RG_BUCK_VBUCK0_SW_OP_EN_ADDR 0x148F
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#define MT6373_RG_BUCK_VBUCK0_RC0_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC1_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC2_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC3_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC4_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC5_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC6_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC7_OP_CFG_ADDR 0x1490
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#define MT6373_RG_BUCK_VBUCK0_RC8_OP_CFG_ADDR 0x1491
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#define MT6373_RG_BUCK_VBUCK0_RC9_OP_CFG_ADDR 0x1491
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#define MT6373_RG_BUCK_VBUCK0_RC10_OP_CFG_ADDR 0x1491
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#define MT6373_RG_BUCK_VBUCK0_RC11_OP_CFG_ADDR 0x1491
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#define MT6373_RG_BUCK_VBUCK0_RC12_OP_CFG_ADDR 0x1491
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#define MT6373_RG_BUCK_VBUCK0_RC13_OP_CFG_ADDR 0x1491
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#define MT6373_RG_BUCK_VBUCK0_HW0_OP_CFG_ADDR 0x1492
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#define MT6373_RG_BUCK_VBUCK0_HW1_OP_CFG_ADDR 0x1492
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#define MT6373_RG_BUCK_VBUCK0_HW2_OP_CFG_ADDR 0x1492
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#define MT6373_RG_BUCK_VBUCK0_HW3_OP_CFG_ADDR 0x1492
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#define MT6373_RG_BUCK_VBUCK0_RC0_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC1_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC2_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC3_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC4_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC5_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC6_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC7_OP_MODE_ADDR 0x1493
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#define MT6373_RG_BUCK_VBUCK0_RC8_OP_MODE_ADDR 0x1494
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#define MT6373_RG_BUCK_VBUCK0_RC9_OP_MODE_ADDR 0x1494
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#define MT6373_RG_BUCK_VBUCK0_RC10_OP_MODE_ADDR 0x1494
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#define MT6373_RG_BUCK_VBUCK0_RC11_OP_MODE_ADDR 0x1494
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#define MT6373_RG_BUCK_VBUCK0_RC12_OP_MODE_ADDR 0x1494
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#define MT6373_RG_BUCK_VBUCK0_RC13_OP_MODE_ADDR 0x1494
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#define MT6373_RG_BUCK_VBUCK0_HW0_OP_MODE_ADDR 0x1495
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#define MT6373_RG_BUCK_VBUCK0_HW1_OP_MODE_ADDR 0x1495
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#define MT6373_RG_BUCK_VBUCK0_HW2_OP_MODE_ADDR 0x1495
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#define MT6373_RG_BUCK_VBUCK0_HW3_OP_MODE_ADDR 0x1495
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#define MT6373_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR 0x1507
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#define MT6373_RG_BUCK_VBUCK1_ONLV_EN_ADDR 0x1508
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#define MT6373_RG_BUCK_VBUCK1_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR 0x150D
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#define MT6373_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR 0x150E
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#define MT6373_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR 0x150E
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#define MT6373_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR 0x150E
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#define MT6373_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR 0x150E
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#define MT6373_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR 0x150E
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#define MT6373_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR 0x150E
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#define MT6373_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x150F
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#define MT6373_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x150F
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#define MT6373_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x150F
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#define MT6373_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x150F
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#define MT6373_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x150F
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#define MT6373_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR 0x1510
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#define MT6373_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR 0x1511
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#define MT6373_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR 0x1511
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#define MT6373_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR 0x1511
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#define MT6373_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR 0x1511
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#define MT6373_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR 0x1511
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#define MT6373_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR 0x1511
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#define MT6373_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1512
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#define MT6373_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1512
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#define MT6373_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1512
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#define MT6373_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1512
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#define MT6373_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR 0x1513
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#define MT6373_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR 0x1514
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#define MT6373_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR 0x1514
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#define MT6373_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR 0x1514
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#define MT6373_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR 0x1514
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#define MT6373_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR 0x1514
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#define MT6373_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR 0x1514
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#define MT6373_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1515
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#define MT6373_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1515
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#define MT6373_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1515
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#define MT6373_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1515
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#define MT6373_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR 0x1587
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#define MT6373_RG_BUCK_VBUCK2_ONLV_EN_ADDR 0x1588
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#define MT6373_RG_BUCK_VBUCK2_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR 0x158D
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#define MT6373_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR 0x158E
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#define MT6373_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR 0x158E
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#define MT6373_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR 0x158E
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#define MT6373_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR 0x158E
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#define MT6373_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR 0x158E
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#define MT6373_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR 0x158E
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#define MT6373_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x158F
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#define MT6373_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x158F
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#define MT6373_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x158F
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#define MT6373_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x158F
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#define MT6373_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x158F
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#define MT6373_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR 0x1590
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#define MT6373_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR 0x1591
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#define MT6373_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR 0x1591
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#define MT6373_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR 0x1591
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#define MT6373_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR 0x1591
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#define MT6373_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR 0x1591
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#define MT6373_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR 0x1591
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#define MT6373_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1592
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#define MT6373_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1592
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#define MT6373_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1592
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#define MT6373_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1592
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#define MT6373_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR 0x1593
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#define MT6373_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR 0x1594
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#define MT6373_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR 0x1594
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#define MT6373_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR 0x1594
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#define MT6373_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR 0x1594
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#define MT6373_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR 0x1594
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#define MT6373_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR 0x1594
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#define MT6373_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1595
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#define MT6373_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1595
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#define MT6373_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1595
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#define MT6373_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1595
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#define MT6373_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR 0x1607
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#define MT6373_RG_BUCK_VBUCK3_ONLV_EN_ADDR 0x1608
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#define MT6373_RG_BUCK_VBUCK3_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR 0x160D
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#define MT6373_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR 0x160E
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#define MT6373_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR 0x160E
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#define MT6373_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR 0x160E
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#define MT6373_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR 0x160E
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#define MT6373_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR 0x160E
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#define MT6373_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR 0x160E
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#define MT6373_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x160F
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#define MT6373_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x160F
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#define MT6373_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x160F
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#define MT6373_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x160F
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#define MT6373_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x160F
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#define MT6373_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR 0x1610
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#define MT6373_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR 0x1611
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#define MT6373_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR 0x1611
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#define MT6373_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR 0x1611
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#define MT6373_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR 0x1611
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#define MT6373_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR 0x1611
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#define MT6373_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR 0x1611
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#define MT6373_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1612
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#define MT6373_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1612
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#define MT6373_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1612
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#define MT6373_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1612
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#define MT6373_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR 0x1613
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#define MT6373_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR 0x1614
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#define MT6373_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR 0x1614
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#define MT6373_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR 0x1614
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#define MT6373_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR 0x1614
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#define MT6373_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR 0x1614
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#define MT6373_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR 0x1614
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#define MT6373_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1615
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#define MT6373_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1615
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#define MT6373_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1615
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#define MT6373_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1615
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#define MT6373_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR 0x1687
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#define MT6373_RG_BUCK_VBUCK4_ONLV_EN_ADDR 0x1688
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#define MT6373_RG_BUCK_VBUCK4_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR 0x168D
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#define MT6373_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR 0x168E
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#define MT6373_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR 0x168E
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#define MT6373_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR 0x168E
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#define MT6373_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR 0x168E
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#define MT6373_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR 0x168E
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#define MT6373_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR 0x168E
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#define MT6373_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x168F
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#define MT6373_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x168F
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#define MT6373_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x168F
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#define MT6373_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x168F
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#define MT6373_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x168F
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#define MT6373_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR 0x1690
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#define MT6373_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR 0x1691
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#define MT6373_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR 0x1691
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#define MT6373_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR 0x1691
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#define MT6373_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR 0x1691
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#define MT6373_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR 0x1691
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#define MT6373_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR 0x1691
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#define MT6373_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1692
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#define MT6373_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1692
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#define MT6373_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1692
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#define MT6373_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1692
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#define MT6373_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR 0x1693
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#define MT6373_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR 0x1694
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#define MT6373_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR 0x1694
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#define MT6373_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR 0x1694
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#define MT6373_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR 0x1694
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#define MT6373_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR 0x1694
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#define MT6373_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR 0x1694
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#define MT6373_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1695
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#define MT6373_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1695
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#define MT6373_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1695
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#define MT6373_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1695
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#define MT6373_RG_BUCK_VBUCK5_VOSEL_SLEEP_ADDR 0x1707
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#define MT6373_RG_BUCK_VBUCK5_ONLV_EN_ADDR 0x1708
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#define MT6373_RG_BUCK_VBUCK5_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK5_RC0_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC1_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC2_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC3_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC4_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC5_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC6_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC7_OP_EN_ADDR 0x170D
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#define MT6373_RG_BUCK_VBUCK5_RC8_OP_EN_ADDR 0x170E
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#define MT6373_RG_BUCK_VBUCK5_RC9_OP_EN_ADDR 0x170E
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#define MT6373_RG_BUCK_VBUCK5_RC10_OP_EN_ADDR 0x170E
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#define MT6373_RG_BUCK_VBUCK5_RC11_OP_EN_ADDR 0x170E
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#define MT6373_RG_BUCK_VBUCK5_RC12_OP_EN_ADDR 0x170E
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#define MT6373_RG_BUCK_VBUCK5_RC13_OP_EN_ADDR 0x170E
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#define MT6373_RG_BUCK_VBUCK5_HW0_OP_EN_ADDR 0x170F
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#define MT6373_RG_BUCK_VBUCK5_HW1_OP_EN_ADDR 0x170F
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#define MT6373_RG_BUCK_VBUCK5_HW2_OP_EN_ADDR 0x170F
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#define MT6373_RG_BUCK_VBUCK5_HW3_OP_EN_ADDR 0x170F
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#define MT6373_RG_BUCK_VBUCK5_SW_OP_EN_ADDR 0x170F
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#define MT6373_RG_BUCK_VBUCK5_RC0_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC1_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC2_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC3_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC4_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC5_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC6_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC7_OP_CFG_ADDR 0x1710
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#define MT6373_RG_BUCK_VBUCK5_RC8_OP_CFG_ADDR 0x1711
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#define MT6373_RG_BUCK_VBUCK5_RC9_OP_CFG_ADDR 0x1711
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#define MT6373_RG_BUCK_VBUCK5_RC10_OP_CFG_ADDR 0x1711
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#define MT6373_RG_BUCK_VBUCK5_RC11_OP_CFG_ADDR 0x1711
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#define MT6373_RG_BUCK_VBUCK5_RC12_OP_CFG_ADDR 0x1711
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#define MT6373_RG_BUCK_VBUCK5_RC13_OP_CFG_ADDR 0x1711
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#define MT6373_RG_BUCK_VBUCK5_HW0_OP_CFG_ADDR 0x1712
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#define MT6373_RG_BUCK_VBUCK5_HW1_OP_CFG_ADDR 0x1712
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#define MT6373_RG_BUCK_VBUCK5_HW2_OP_CFG_ADDR 0x1712
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#define MT6373_RG_BUCK_VBUCK5_HW3_OP_CFG_ADDR 0x1712
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#define MT6373_RG_BUCK_VBUCK5_RC0_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC1_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC2_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC3_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC4_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC5_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC6_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC7_OP_MODE_ADDR 0x1713
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#define MT6373_RG_BUCK_VBUCK5_RC8_OP_MODE_ADDR 0x1714
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#define MT6373_RG_BUCK_VBUCK5_RC9_OP_MODE_ADDR 0x1714
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#define MT6373_RG_BUCK_VBUCK5_RC10_OP_MODE_ADDR 0x1714
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#define MT6373_RG_BUCK_VBUCK5_RC11_OP_MODE_ADDR 0x1714
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#define MT6373_RG_BUCK_VBUCK5_RC12_OP_MODE_ADDR 0x1714
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#define MT6373_RG_BUCK_VBUCK5_RC13_OP_MODE_ADDR 0x1714
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#define MT6373_RG_BUCK_VBUCK5_HW0_OP_MODE_ADDR 0x1715
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#define MT6373_RG_BUCK_VBUCK5_HW1_OP_MODE_ADDR 0x1715
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#define MT6373_RG_BUCK_VBUCK5_HW2_OP_MODE_ADDR 0x1715
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#define MT6373_RG_BUCK_VBUCK5_HW3_OP_MODE_ADDR 0x1715
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#define MT6373_RG_BUCK_VBUCK6_VOSEL_SLEEP_ADDR 0x1787
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#define MT6373_RG_BUCK_VBUCK6_ONLV_EN_ADDR 0x1788
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#define MT6373_RG_BUCK_VBUCK6_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK6_RC0_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC1_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC2_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC3_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC4_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC5_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC6_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC7_OP_EN_ADDR 0x178D
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#define MT6373_RG_BUCK_VBUCK6_RC8_OP_EN_ADDR 0x178E
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#define MT6373_RG_BUCK_VBUCK6_RC9_OP_EN_ADDR 0x178E
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#define MT6373_RG_BUCK_VBUCK6_RC10_OP_EN_ADDR 0x178E
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#define MT6373_RG_BUCK_VBUCK6_RC11_OP_EN_ADDR 0x178E
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#define MT6373_RG_BUCK_VBUCK6_RC12_OP_EN_ADDR 0x178E
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#define MT6373_RG_BUCK_VBUCK6_RC13_OP_EN_ADDR 0x178E
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#define MT6373_RG_BUCK_VBUCK6_HW0_OP_EN_ADDR 0x178F
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#define MT6373_RG_BUCK_VBUCK6_HW1_OP_EN_ADDR 0x178F
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#define MT6373_RG_BUCK_VBUCK6_HW2_OP_EN_ADDR 0x178F
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#define MT6373_RG_BUCK_VBUCK6_HW3_OP_EN_ADDR 0x178F
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#define MT6373_RG_BUCK_VBUCK6_SW_OP_EN_ADDR 0x178F
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#define MT6373_RG_BUCK_VBUCK6_RC0_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC1_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC2_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC3_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC4_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC5_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC6_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC7_OP_CFG_ADDR 0x1790
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#define MT6373_RG_BUCK_VBUCK6_RC8_OP_CFG_ADDR 0x1791
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#define MT6373_RG_BUCK_VBUCK6_RC9_OP_CFG_ADDR 0x1791
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#define MT6373_RG_BUCK_VBUCK6_RC10_OP_CFG_ADDR 0x1791
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#define MT6373_RG_BUCK_VBUCK6_RC11_OP_CFG_ADDR 0x1791
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#define MT6373_RG_BUCK_VBUCK6_RC12_OP_CFG_ADDR 0x1791
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#define MT6373_RG_BUCK_VBUCK6_RC13_OP_CFG_ADDR 0x1791
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#define MT6373_RG_BUCK_VBUCK6_HW0_OP_CFG_ADDR 0x1792
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#define MT6373_RG_BUCK_VBUCK6_HW1_OP_CFG_ADDR 0x1792
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#define MT6373_RG_BUCK_VBUCK6_HW2_OP_CFG_ADDR 0x1792
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#define MT6373_RG_BUCK_VBUCK6_HW3_OP_CFG_ADDR 0x1792
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#define MT6373_RG_BUCK_VBUCK6_RC0_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC1_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC2_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC3_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC4_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC5_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC6_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC7_OP_MODE_ADDR 0x1793
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#define MT6373_RG_BUCK_VBUCK6_RC8_OP_MODE_ADDR 0x1794
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#define MT6373_RG_BUCK_VBUCK6_RC9_OP_MODE_ADDR 0x1794
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#define MT6373_RG_BUCK_VBUCK6_RC10_OP_MODE_ADDR 0x1794
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#define MT6373_RG_BUCK_VBUCK6_RC11_OP_MODE_ADDR 0x1794
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#define MT6373_RG_BUCK_VBUCK6_RC12_OP_MODE_ADDR 0x1794
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#define MT6373_RG_BUCK_VBUCK6_RC13_OP_MODE_ADDR 0x1794
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#define MT6373_RG_BUCK_VBUCK6_HW0_OP_MODE_ADDR 0x1795
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#define MT6373_RG_BUCK_VBUCK6_HW1_OP_MODE_ADDR 0x1795
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#define MT6373_RG_BUCK_VBUCK6_HW2_OP_MODE_ADDR 0x1795
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#define MT6373_RG_BUCK_VBUCK6_HW3_OP_MODE_ADDR 0x1795
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#define MT6373_RG_BUCK_VBUCK7_VOSEL_SLEEP_ADDR 0x1807
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#define MT6373_RG_BUCK_VBUCK7_ONLV_EN_ADDR 0x1808
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|
#define MT6373_RG_BUCK_VBUCK7_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK7_RC0_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC1_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC2_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC3_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC4_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC5_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC6_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC7_OP_EN_ADDR 0x180D
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#define MT6373_RG_BUCK_VBUCK7_RC8_OP_EN_ADDR 0x180E
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#define MT6373_RG_BUCK_VBUCK7_RC9_OP_EN_ADDR 0x180E
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#define MT6373_RG_BUCK_VBUCK7_RC10_OP_EN_ADDR 0x180E
|
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#define MT6373_RG_BUCK_VBUCK7_RC11_OP_EN_ADDR 0x180E
|
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#define MT6373_RG_BUCK_VBUCK7_RC12_OP_EN_ADDR 0x180E
|
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#define MT6373_RG_BUCK_VBUCK7_RC13_OP_EN_ADDR 0x180E
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#define MT6373_RG_BUCK_VBUCK7_HW0_OP_EN_ADDR 0x180F
|
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#define MT6373_RG_BUCK_VBUCK7_HW1_OP_EN_ADDR 0x180F
|
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#define MT6373_RG_BUCK_VBUCK7_HW2_OP_EN_ADDR 0x180F
|
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#define MT6373_RG_BUCK_VBUCK7_HW3_OP_EN_ADDR 0x180F
|
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#define MT6373_RG_BUCK_VBUCK7_SW_OP_EN_ADDR 0x180F
|
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#define MT6373_RG_BUCK_VBUCK7_RC0_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC1_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC2_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC3_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC4_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC5_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC6_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC7_OP_CFG_ADDR 0x1810
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#define MT6373_RG_BUCK_VBUCK7_RC8_OP_CFG_ADDR 0x1811
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#define MT6373_RG_BUCK_VBUCK7_RC9_OP_CFG_ADDR 0x1811
|
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#define MT6373_RG_BUCK_VBUCK7_RC10_OP_CFG_ADDR 0x1811
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#define MT6373_RG_BUCK_VBUCK7_RC11_OP_CFG_ADDR 0x1811
|
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#define MT6373_RG_BUCK_VBUCK7_RC12_OP_CFG_ADDR 0x1811
|
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#define MT6373_RG_BUCK_VBUCK7_RC13_OP_CFG_ADDR 0x1811
|
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#define MT6373_RG_BUCK_VBUCK7_HW0_OP_CFG_ADDR 0x1812
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#define MT6373_RG_BUCK_VBUCK7_HW1_OP_CFG_ADDR 0x1812
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#define MT6373_RG_BUCK_VBUCK7_HW2_OP_CFG_ADDR 0x1812
|
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#define MT6373_RG_BUCK_VBUCK7_HW3_OP_CFG_ADDR 0x1812
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#define MT6373_RG_BUCK_VBUCK7_RC0_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC1_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC2_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC3_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC4_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC5_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC6_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC7_OP_MODE_ADDR 0x1813
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#define MT6373_RG_BUCK_VBUCK7_RC8_OP_MODE_ADDR 0x1814
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#define MT6373_RG_BUCK_VBUCK7_RC9_OP_MODE_ADDR 0x1814
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#define MT6373_RG_BUCK_VBUCK7_RC10_OP_MODE_ADDR 0x1814
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#define MT6373_RG_BUCK_VBUCK7_RC11_OP_MODE_ADDR 0x1814
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#define MT6373_RG_BUCK_VBUCK7_RC12_OP_MODE_ADDR 0x1814
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#define MT6373_RG_BUCK_VBUCK7_RC13_OP_MODE_ADDR 0x1814
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#define MT6373_RG_BUCK_VBUCK7_HW0_OP_MODE_ADDR 0x1815
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#define MT6373_RG_BUCK_VBUCK7_HW1_OP_MODE_ADDR 0x1815
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#define MT6373_RG_BUCK_VBUCK7_HW2_OP_MODE_ADDR 0x1815
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#define MT6373_RG_BUCK_VBUCK7_HW3_OP_MODE_ADDR 0x1815
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#define MT6373_RG_BUCK_VBUCK8_VOSEL_SLEEP_ADDR 0x1887
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#define MT6373_RG_BUCK_VBUCK8_ONLV_EN_ADDR 0x1888
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#define MT6373_RG_BUCK_VBUCK8_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK8_RC0_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC1_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC2_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC3_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC4_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC5_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC6_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC7_OP_EN_ADDR 0x188D
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#define MT6373_RG_BUCK_VBUCK8_RC8_OP_EN_ADDR 0x188E
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#define MT6373_RG_BUCK_VBUCK8_RC9_OP_EN_ADDR 0x188E
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#define MT6373_RG_BUCK_VBUCK8_RC10_OP_EN_ADDR 0x188E
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#define MT6373_RG_BUCK_VBUCK8_RC11_OP_EN_ADDR 0x188E
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#define MT6373_RG_BUCK_VBUCK8_RC12_OP_EN_ADDR 0x188E
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#define MT6373_RG_BUCK_VBUCK8_RC13_OP_EN_ADDR 0x188E
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#define MT6373_RG_BUCK_VBUCK8_HW0_OP_EN_ADDR 0x188F
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#define MT6373_RG_BUCK_VBUCK8_HW1_OP_EN_ADDR 0x188F
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#define MT6373_RG_BUCK_VBUCK8_HW2_OP_EN_ADDR 0x188F
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#define MT6373_RG_BUCK_VBUCK8_HW3_OP_EN_ADDR 0x188F
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#define MT6373_RG_BUCK_VBUCK8_SW_OP_EN_ADDR 0x188F
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#define MT6373_RG_BUCK_VBUCK8_RC0_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC1_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC2_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC3_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC4_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC5_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC6_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC7_OP_CFG_ADDR 0x1890
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#define MT6373_RG_BUCK_VBUCK8_RC8_OP_CFG_ADDR 0x1891
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#define MT6373_RG_BUCK_VBUCK8_RC9_OP_CFG_ADDR 0x1891
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#define MT6373_RG_BUCK_VBUCK8_RC10_OP_CFG_ADDR 0x1891
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#define MT6373_RG_BUCK_VBUCK8_RC11_OP_CFG_ADDR 0x1891
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#define MT6373_RG_BUCK_VBUCK8_RC12_OP_CFG_ADDR 0x1891
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#define MT6373_RG_BUCK_VBUCK8_RC13_OP_CFG_ADDR 0x1891
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#define MT6373_RG_BUCK_VBUCK8_HW0_OP_CFG_ADDR 0x1892
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#define MT6373_RG_BUCK_VBUCK8_HW1_OP_CFG_ADDR 0x1892
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#define MT6373_RG_BUCK_VBUCK8_HW2_OP_CFG_ADDR 0x1892
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#define MT6373_RG_BUCK_VBUCK8_HW3_OP_CFG_ADDR 0x1892
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#define MT6373_RG_BUCK_VBUCK8_RC0_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC1_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC2_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC3_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC4_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC5_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC6_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC7_OP_MODE_ADDR 0x1893
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#define MT6373_RG_BUCK_VBUCK8_RC8_OP_MODE_ADDR 0x1894
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#define MT6373_RG_BUCK_VBUCK8_RC9_OP_MODE_ADDR 0x1894
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#define MT6373_RG_BUCK_VBUCK8_RC10_OP_MODE_ADDR 0x1894
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#define MT6373_RG_BUCK_VBUCK8_RC11_OP_MODE_ADDR 0x1894
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#define MT6373_RG_BUCK_VBUCK8_RC12_OP_MODE_ADDR 0x1894
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#define MT6373_RG_BUCK_VBUCK8_RC13_OP_MODE_ADDR 0x1894
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#define MT6373_RG_BUCK_VBUCK8_HW0_OP_MODE_ADDR 0x1895
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#define MT6373_RG_BUCK_VBUCK8_HW1_OP_MODE_ADDR 0x1895
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#define MT6373_RG_BUCK_VBUCK8_HW2_OP_MODE_ADDR 0x1895
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#define MT6373_RG_BUCK_VBUCK8_HW3_OP_MODE_ADDR 0x1895
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#define MT6373_RG_BUCK_VBUCK9_VOSEL_SLEEP_ADDR 0x1907
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#define MT6373_RG_BUCK_VBUCK9_ONLV_EN_ADDR 0x1908
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#define MT6373_RG_BUCK_VBUCK9_ONLV_EN_SHIFT 4
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#define MT6373_RG_BUCK_VBUCK9_RC0_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC1_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC2_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC3_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC4_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC5_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC6_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC7_OP_EN_ADDR 0x190D
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#define MT6373_RG_BUCK_VBUCK9_RC8_OP_EN_ADDR 0x190E
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#define MT6373_RG_BUCK_VBUCK9_RC9_OP_EN_ADDR 0x190E
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#define MT6373_RG_BUCK_VBUCK9_RC10_OP_EN_ADDR 0x190E
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#define MT6373_RG_BUCK_VBUCK9_RC11_OP_EN_ADDR 0x190E
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#define MT6373_RG_BUCK_VBUCK9_RC12_OP_EN_ADDR 0x190E
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#define MT6373_RG_BUCK_VBUCK9_RC13_OP_EN_ADDR 0x190E
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#define MT6373_RG_BUCK_VBUCK9_HW0_OP_EN_ADDR 0x190F
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#define MT6373_RG_BUCK_VBUCK9_HW1_OP_EN_ADDR 0x190F
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#define MT6373_RG_BUCK_VBUCK9_HW2_OP_EN_ADDR 0x190F
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#define MT6373_RG_BUCK_VBUCK9_HW3_OP_EN_ADDR 0x190F
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#define MT6373_RG_BUCK_VBUCK9_SW_OP_EN_ADDR 0x190F
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#define MT6373_RG_BUCK_VBUCK9_RC0_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC1_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC2_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC3_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC4_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC5_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC6_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC7_OP_CFG_ADDR 0x1910
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#define MT6373_RG_BUCK_VBUCK9_RC8_OP_CFG_ADDR 0x1911
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#define MT6373_RG_BUCK_VBUCK9_RC9_OP_CFG_ADDR 0x1911
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#define MT6373_RG_BUCK_VBUCK9_RC10_OP_CFG_ADDR 0x1911
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#define MT6373_RG_BUCK_VBUCK9_RC11_OP_CFG_ADDR 0x1911
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#define MT6373_RG_BUCK_VBUCK9_RC12_OP_CFG_ADDR 0x1911
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#define MT6373_RG_BUCK_VBUCK9_RC13_OP_CFG_ADDR 0x1911
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#define MT6373_RG_BUCK_VBUCK9_HW0_OP_CFG_ADDR 0x1912
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#define MT6373_RG_BUCK_VBUCK9_HW1_OP_CFG_ADDR 0x1912
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#define MT6373_RG_BUCK_VBUCK9_HW2_OP_CFG_ADDR 0x1912
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#define MT6373_RG_BUCK_VBUCK9_HW3_OP_CFG_ADDR 0x1912
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#define MT6373_RG_BUCK_VBUCK9_RC0_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC1_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC2_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC3_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC4_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC5_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC6_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC7_OP_MODE_ADDR 0x1913
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#define MT6373_RG_BUCK_VBUCK9_RC8_OP_MODE_ADDR 0x1914
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#define MT6373_RG_BUCK_VBUCK9_RC9_OP_MODE_ADDR 0x1914
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#define MT6373_RG_BUCK_VBUCK9_RC10_OP_MODE_ADDR 0x1914
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#define MT6373_RG_BUCK_VBUCK9_RC11_OP_MODE_ADDR 0x1914
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#define MT6373_RG_BUCK_VBUCK9_RC12_OP_MODE_ADDR 0x1914
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#define MT6373_RG_BUCK_VBUCK9_RC13_OP_MODE_ADDR 0x1914
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#define MT6373_RG_BUCK_VBUCK9_HW0_OP_MODE_ADDR 0x1915
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#define MT6373_RG_BUCK_VBUCK9_HW1_OP_MODE_ADDR 0x1915
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#define MT6373_RG_BUCK_VBUCK9_HW2_OP_MODE_ADDR 0x1915
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#define MT6373_RG_BUCK_VBUCK9_HW3_OP_MODE_ADDR 0x1915
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#define MT6373_RG_LDO_VAUD18_ONLV_EN_ADDR 0x1B88
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#define MT6373_RG_LDO_VAUD18_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VAUD18_RC0_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC1_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC2_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC3_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC4_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC5_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC6_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC7_OP_EN_ADDR 0x1B8C
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#define MT6373_RG_LDO_VAUD18_RC8_OP_EN_ADDR 0x1B8D
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#define MT6373_RG_LDO_VAUD18_RC9_OP_EN_ADDR 0x1B8D
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#define MT6373_RG_LDO_VAUD18_RC10_OP_EN_ADDR 0x1B8D
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#define MT6373_RG_LDO_VAUD18_RC11_OP_EN_ADDR 0x1B8D
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#define MT6373_RG_LDO_VAUD18_RC12_OP_EN_ADDR 0x1B8D
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#define MT6373_RG_LDO_VAUD18_RC13_OP_EN_ADDR 0x1B8D
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#define MT6373_RG_LDO_VAUD18_HW0_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_HW1_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_HW2_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_HW3_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_HW4_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_HW5_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_HW6_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_SW_OP_EN_ADDR 0x1B8E
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#define MT6373_RG_LDO_VAUD18_RC0_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC1_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC2_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC3_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC4_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC5_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC6_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC7_OP_CFG_ADDR 0x1B8F
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#define MT6373_RG_LDO_VAUD18_RC8_OP_CFG_ADDR 0x1B90
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#define MT6373_RG_LDO_VAUD18_RC9_OP_CFG_ADDR 0x1B90
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#define MT6373_RG_LDO_VAUD18_RC10_OP_CFG_ADDR 0x1B90
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#define MT6373_RG_LDO_VAUD18_RC11_OP_CFG_ADDR 0x1B90
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#define MT6373_RG_LDO_VAUD18_RC12_OP_CFG_ADDR 0x1B90
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#define MT6373_RG_LDO_VAUD18_RC13_OP_CFG_ADDR 0x1B90
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#define MT6373_RG_LDO_VAUD18_HW0_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_HW1_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_HW2_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_HW3_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_HW4_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_HW5_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_HW6_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_SW_OP_CFG_ADDR 0x1B91
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#define MT6373_RG_LDO_VAUD18_RC0_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC1_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC2_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC3_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC4_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC5_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC6_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC7_OP_MODE_ADDR 0x1B92
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#define MT6373_RG_LDO_VAUD18_RC8_OP_MODE_ADDR 0x1B93
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#define MT6373_RG_LDO_VAUD18_RC9_OP_MODE_ADDR 0x1B93
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#define MT6373_RG_LDO_VAUD18_RC10_OP_MODE_ADDR 0x1B93
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#define MT6373_RG_LDO_VAUD18_RC11_OP_MODE_ADDR 0x1B93
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#define MT6373_RG_LDO_VAUD18_RC12_OP_MODE_ADDR 0x1B93
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#define MT6373_RG_LDO_VAUD18_RC13_OP_MODE_ADDR 0x1B93
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#define MT6373_RG_LDO_VAUD18_HW0_OP_MODE_ADDR 0x1B94
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#define MT6373_RG_LDO_VAUD18_HW1_OP_MODE_ADDR 0x1B94
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#define MT6373_RG_LDO_VAUD18_HW2_OP_MODE_ADDR 0x1B94
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#define MT6373_RG_LDO_VAUD18_HW3_OP_MODE_ADDR 0x1B94
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#define MT6373_RG_LDO_VAUD18_HW4_OP_MODE_ADDR 0x1B94
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#define MT6373_RG_LDO_VAUD18_HW5_OP_MODE_ADDR 0x1B94
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#define MT6373_RG_LDO_VAUD18_HW6_OP_MODE_ADDR 0x1B94
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#define MT6373_RG_LDO_VUSB_ONLV_EN_ADDR 0x1B96
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#define MT6373_RG_LDO_VUSB_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VUSB_RC0_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC1_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC2_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC3_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC4_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC5_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC6_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC7_OP_EN_ADDR 0x1B9A
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#define MT6373_RG_LDO_VUSB_RC8_OP_EN_ADDR 0x1B9B
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#define MT6373_RG_LDO_VUSB_RC9_OP_EN_ADDR 0x1B9B
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#define MT6373_RG_LDO_VUSB_RC10_OP_EN_ADDR 0x1B9B
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#define MT6373_RG_LDO_VUSB_RC11_OP_EN_ADDR 0x1B9B
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#define MT6373_RG_LDO_VUSB_RC12_OP_EN_ADDR 0x1B9B
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#define MT6373_RG_LDO_VUSB_RC13_OP_EN_ADDR 0x1B9B
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#define MT6373_RG_LDO_VUSB_HW0_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_HW1_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_HW2_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_HW3_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_HW4_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_HW5_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_HW6_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_SW_OP_EN_ADDR 0x1B9C
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#define MT6373_RG_LDO_VUSB_RC0_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC1_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC2_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC3_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC4_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC5_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC6_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC7_OP_CFG_ADDR 0x1B9D
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#define MT6373_RG_LDO_VUSB_RC8_OP_CFG_ADDR 0x1B9E
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#define MT6373_RG_LDO_VUSB_RC9_OP_CFG_ADDR 0x1B9E
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#define MT6373_RG_LDO_VUSB_RC10_OP_CFG_ADDR 0x1B9E
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#define MT6373_RG_LDO_VUSB_RC11_OP_CFG_ADDR 0x1B9E
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#define MT6373_RG_LDO_VUSB_RC12_OP_CFG_ADDR 0x1B9E
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#define MT6373_RG_LDO_VUSB_RC13_OP_CFG_ADDR 0x1B9E
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#define MT6373_RG_LDO_VUSB_HW0_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_HW1_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_HW2_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_HW3_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_HW4_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_HW5_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_HW6_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_SW_OP_CFG_ADDR 0x1B9F
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#define MT6373_RG_LDO_VUSB_RC0_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC1_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC2_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC3_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC4_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC5_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC6_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC7_OP_MODE_ADDR 0x1BA0
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#define MT6373_RG_LDO_VUSB_RC8_OP_MODE_ADDR 0x1BA1
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#define MT6373_RG_LDO_VUSB_RC9_OP_MODE_ADDR 0x1BA1
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#define MT6373_RG_LDO_VUSB_RC10_OP_MODE_ADDR 0x1BA1
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#define MT6373_RG_LDO_VUSB_RC11_OP_MODE_ADDR 0x1BA1
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#define MT6373_RG_LDO_VUSB_RC12_OP_MODE_ADDR 0x1BA1
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#define MT6373_RG_LDO_VUSB_RC13_OP_MODE_ADDR 0x1BA1
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#define MT6373_RG_LDO_VUSB_HW0_OP_MODE_ADDR 0x1BA2
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#define MT6373_RG_LDO_VUSB_HW1_OP_MODE_ADDR 0x1BA2
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#define MT6373_RG_LDO_VUSB_HW2_OP_MODE_ADDR 0x1BA2
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#define MT6373_RG_LDO_VUSB_HW3_OP_MODE_ADDR 0x1BA2
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#define MT6373_RG_LDO_VUSB_HW4_OP_MODE_ADDR 0x1BA2
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#define MT6373_RG_LDO_VUSB_HW5_OP_MODE_ADDR 0x1BA2
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#define MT6373_RG_LDO_VUSB_HW6_OP_MODE_ADDR 0x1BA2
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#define MT6373_RG_LDO_VAUX18_ONLV_EN_ADDR 0x1BA4
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#define MT6373_RG_LDO_VAUX18_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VAUX18_RC0_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC1_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC2_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC3_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC4_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC5_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC6_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC7_OP_EN_ADDR 0x1BA8
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#define MT6373_RG_LDO_VAUX18_RC8_OP_EN_ADDR 0x1BA9
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#define MT6373_RG_LDO_VAUX18_RC9_OP_EN_ADDR 0x1BA9
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#define MT6373_RG_LDO_VAUX18_RC10_OP_EN_ADDR 0x1BA9
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#define MT6373_RG_LDO_VAUX18_RC11_OP_EN_ADDR 0x1BA9
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#define MT6373_RG_LDO_VAUX18_RC12_OP_EN_ADDR 0x1BA9
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#define MT6373_RG_LDO_VAUX18_RC13_OP_EN_ADDR 0x1BA9
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#define MT6373_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1BAA
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#define MT6373_RG_LDO_VAUX18_RC0_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC1_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC2_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC3_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC4_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC5_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC6_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC7_OP_CFG_ADDR 0x1BAB
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#define MT6373_RG_LDO_VAUX18_RC8_OP_CFG_ADDR 0x1BAC
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#define MT6373_RG_LDO_VAUX18_RC9_OP_CFG_ADDR 0x1BAC
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#define MT6373_RG_LDO_VAUX18_RC10_OP_CFG_ADDR 0x1BAC
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#define MT6373_RG_LDO_VAUX18_RC11_OP_CFG_ADDR 0x1BAC
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#define MT6373_RG_LDO_VAUX18_RC12_OP_CFG_ADDR 0x1BAC
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#define MT6373_RG_LDO_VAUX18_RC13_OP_CFG_ADDR 0x1BAC
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#define MT6373_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1BAD
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#define MT6373_RG_LDO_VAUX18_RC0_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC1_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC2_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC3_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC4_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC5_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC6_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC7_OP_MODE_ADDR 0x1BAE
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#define MT6373_RG_LDO_VAUX18_RC8_OP_MODE_ADDR 0x1BAF
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#define MT6373_RG_LDO_VAUX18_RC9_OP_MODE_ADDR 0x1BAF
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#define MT6373_RG_LDO_VAUX18_RC10_OP_MODE_ADDR 0x1BAF
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#define MT6373_RG_LDO_VAUX18_RC11_OP_MODE_ADDR 0x1BAF
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#define MT6373_RG_LDO_VAUX18_RC12_OP_MODE_ADDR 0x1BAF
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#define MT6373_RG_LDO_VAUX18_RC13_OP_MODE_ADDR 0x1BAF
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#define MT6373_RG_LDO_VAUX18_HW0_OP_MODE_ADDR 0x1BB0
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#define MT6373_RG_LDO_VAUX18_HW1_OP_MODE_ADDR 0x1BB0
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#define MT6373_RG_LDO_VAUX18_HW2_OP_MODE_ADDR 0x1BB0
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#define MT6373_RG_LDO_VAUX18_HW3_OP_MODE_ADDR 0x1BB0
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#define MT6373_RG_LDO_VAUX18_HW4_OP_MODE_ADDR 0x1BB0
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#define MT6373_RG_LDO_VAUX18_HW5_OP_MODE_ADDR 0x1BB0
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#define MT6373_RG_LDO_VAUX18_HW6_OP_MODE_ADDR 0x1BB0
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#define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_ADDR 0x1BB2
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#define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_EN_ADDR 0x1BB6
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#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_EN_ADDR 0x1BB7
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#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_EN_ADDR 0x1BB7
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#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_EN_ADDR 0x1BB7
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#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_EN_ADDR 0x1BB7
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#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_EN_ADDR 0x1BB7
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#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_EN_ADDR 0x1BB7
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#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_SW_OP_EN_ADDR 0x1BB8
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#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_CFG_ADDR 0x1BB9
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#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_CFG_ADDR 0x1BBA
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#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_CFG_ADDR 0x1BBA
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#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_CFG_ADDR 0x1BBA
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#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_CFG_ADDR 0x1BBA
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#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_CFG_ADDR 0x1BBA
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#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_CFG_ADDR 0x1BBA
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#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_SW_OP_CFG_ADDR 0x1BBB
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#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_MODE_ADDR 0x1BBC
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#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_MODE_ADDR 0x1BBD
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#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_MODE_ADDR 0x1BBD
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#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_MODE_ADDR 0x1BBD
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#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_MODE_ADDR 0x1BBD
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#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_MODE_ADDR 0x1BBD
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#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_MODE_ADDR 0x1BBD
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#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_MODE_ADDR 0x1BBE
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#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_MODE_ADDR 0x1BBE
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#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_MODE_ADDR 0x1BBE
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#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_MODE_ADDR 0x1BBE
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#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_MODE_ADDR 0x1BBE
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#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_MODE_ADDR 0x1BBE
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#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_MODE_ADDR 0x1BBE
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#define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_ADDR 0x1BC0
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#define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_EN_ADDR 0x1BC4
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#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_EN_ADDR 0x1BC5
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#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_EN_ADDR 0x1BC5
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#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_EN_ADDR 0x1BC5
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#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_EN_ADDR 0x1BC5
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#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_EN_ADDR 0x1BC5
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#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_EN_ADDR 0x1BC5
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#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_SW_OP_EN_ADDR 0x1BC6
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#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_CFG_ADDR 0x1BC7
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#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_CFG_ADDR 0x1BC8
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#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_CFG_ADDR 0x1BC8
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#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_CFG_ADDR 0x1BC8
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#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_CFG_ADDR 0x1BC8
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#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_CFG_ADDR 0x1BC8
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#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_CFG_ADDR 0x1BC8
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#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_SW_OP_CFG_ADDR 0x1BC9
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#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_MODE_ADDR 0x1BCA
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#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_MODE_ADDR 0x1BCB
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#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_MODE_ADDR 0x1BCB
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#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_MODE_ADDR 0x1BCB
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#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_MODE_ADDR 0x1BCB
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#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_MODE_ADDR 0x1BCB
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#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_MODE_ADDR 0x1BCB
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#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_MODE_ADDR 0x1BCC
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#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_MODE_ADDR 0x1BCC
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#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_MODE_ADDR 0x1BCC
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#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_MODE_ADDR 0x1BCC
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#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_MODE_ADDR 0x1BCC
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#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_MODE_ADDR 0x1BCC
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#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_MODE_ADDR 0x1BCC
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#define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_ADDR 0x1BCE
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#define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_EN_ADDR 0x1BD2
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#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_EN_ADDR 0x1BD3
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#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_EN_ADDR 0x1BD3
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#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_EN_ADDR 0x1BD3
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#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_EN_ADDR 0x1BD3
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#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_EN_ADDR 0x1BD3
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#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_EN_ADDR 0x1BD3
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#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_EN_ADDR 0x1BD4
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#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_CFG_ADDR 0x1BD5
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#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_CFG_ADDR 0x1BD6
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#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_CFG_ADDR 0x1BD6
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#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_CFG_ADDR 0x1BD6
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#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_CFG_ADDR 0x1BD6
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#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_CFG_ADDR 0x1BD6
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#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_CFG_ADDR 0x1BD6
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#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_CFG_ADDR 0x1BD7
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#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_MODE_ADDR 0x1BD8
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#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_MODE_ADDR 0x1BD9
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#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_MODE_ADDR 0x1BD9
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#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_MODE_ADDR 0x1BD9
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#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_MODE_ADDR 0x1BD9
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#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_MODE_ADDR 0x1BD9
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#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_MODE_ADDR 0x1BD9
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#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_MODE_ADDR 0x1BDA
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#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_MODE_ADDR 0x1BDA
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#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_MODE_ADDR 0x1BDA
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#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_MODE_ADDR 0x1BDA
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#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_MODE_ADDR 0x1BDA
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#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_MODE_ADDR 0x1BDA
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#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_MODE_ADDR 0x1BDA
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#define MT6373_RG_LDO_VCN33_1_ONLV_EN_ADDR 0x1C08
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#define MT6373_RG_LDO_VCN33_1_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VCN33_1_RC0_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC1_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC2_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC3_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC4_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC5_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC6_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC7_OP_EN_ADDR 0x1C0C
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#define MT6373_RG_LDO_VCN33_1_RC8_OP_EN_ADDR 0x1C0D
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#define MT6373_RG_LDO_VCN33_1_RC9_OP_EN_ADDR 0x1C0D
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#define MT6373_RG_LDO_VCN33_1_RC10_OP_EN_ADDR 0x1C0D
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#define MT6373_RG_LDO_VCN33_1_RC11_OP_EN_ADDR 0x1C0D
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#define MT6373_RG_LDO_VCN33_1_RC12_OP_EN_ADDR 0x1C0D
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#define MT6373_RG_LDO_VCN33_1_RC13_OP_EN_ADDR 0x1C0D
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#define MT6373_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_HW1_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_HW2_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_HW3_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_HW4_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_HW5_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_HW6_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_SW_OP_EN_ADDR 0x1C0E
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#define MT6373_RG_LDO_VCN33_1_RC0_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC1_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC2_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC3_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC4_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC5_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC6_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC7_OP_CFG_ADDR 0x1C0F
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#define MT6373_RG_LDO_VCN33_1_RC8_OP_CFG_ADDR 0x1C10
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#define MT6373_RG_LDO_VCN33_1_RC9_OP_CFG_ADDR 0x1C10
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#define MT6373_RG_LDO_VCN33_1_RC10_OP_CFG_ADDR 0x1C10
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#define MT6373_RG_LDO_VCN33_1_RC11_OP_CFG_ADDR 0x1C10
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#define MT6373_RG_LDO_VCN33_1_RC12_OP_CFG_ADDR 0x1C10
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#define MT6373_RG_LDO_VCN33_1_RC13_OP_CFG_ADDR 0x1C10
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#define MT6373_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_SW_OP_CFG_ADDR 0x1C11
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#define MT6373_RG_LDO_VCN33_1_RC0_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC1_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC2_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC3_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC4_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC5_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC6_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC7_OP_MODE_ADDR 0x1C12
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#define MT6373_RG_LDO_VCN33_1_RC8_OP_MODE_ADDR 0x1C13
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#define MT6373_RG_LDO_VCN33_1_RC9_OP_MODE_ADDR 0x1C13
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#define MT6373_RG_LDO_VCN33_1_RC10_OP_MODE_ADDR 0x1C13
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#define MT6373_RG_LDO_VCN33_1_RC11_OP_MODE_ADDR 0x1C13
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#define MT6373_RG_LDO_VCN33_1_RC12_OP_MODE_ADDR 0x1C13
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#define MT6373_RG_LDO_VCN33_1_RC13_OP_MODE_ADDR 0x1C13
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#define MT6373_RG_LDO_VCN33_1_HW0_OP_MODE_ADDR 0x1C14
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#define MT6373_RG_LDO_VCN33_1_HW1_OP_MODE_ADDR 0x1C14
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#define MT6373_RG_LDO_VCN33_1_HW2_OP_MODE_ADDR 0x1C14
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#define MT6373_RG_LDO_VCN33_1_HW3_OP_MODE_ADDR 0x1C14
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#define MT6373_RG_LDO_VCN33_1_HW4_OP_MODE_ADDR 0x1C14
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#define MT6373_RG_LDO_VCN33_1_HW5_OP_MODE_ADDR 0x1C14
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#define MT6373_RG_LDO_VCN33_1_HW6_OP_MODE_ADDR 0x1C14
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#define MT6373_RG_LDO_VCN33_2_ONLV_EN_ADDR 0x1C16
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#define MT6373_RG_LDO_VCN33_2_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VCN33_2_RC0_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC1_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC2_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC3_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC4_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC5_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC6_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC7_OP_EN_ADDR 0x1C1A
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#define MT6373_RG_LDO_VCN33_2_RC8_OP_EN_ADDR 0x1C1B
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#define MT6373_RG_LDO_VCN33_2_RC9_OP_EN_ADDR 0x1C1B
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#define MT6373_RG_LDO_VCN33_2_RC10_OP_EN_ADDR 0x1C1B
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#define MT6373_RG_LDO_VCN33_2_RC11_OP_EN_ADDR 0x1C1B
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#define MT6373_RG_LDO_VCN33_2_RC12_OP_EN_ADDR 0x1C1B
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#define MT6373_RG_LDO_VCN33_2_RC13_OP_EN_ADDR 0x1C1B
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#define MT6373_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_HW1_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_HW2_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_HW3_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_HW4_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_HW5_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_HW6_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_SW_OP_EN_ADDR 0x1C1C
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#define MT6373_RG_LDO_VCN33_2_RC0_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC1_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC2_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC3_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC4_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC5_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC6_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC7_OP_CFG_ADDR 0x1C1D
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#define MT6373_RG_LDO_VCN33_2_RC8_OP_CFG_ADDR 0x1C1E
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#define MT6373_RG_LDO_VCN33_2_RC9_OP_CFG_ADDR 0x1C1E
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#define MT6373_RG_LDO_VCN33_2_RC10_OP_CFG_ADDR 0x1C1E
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#define MT6373_RG_LDO_VCN33_2_RC11_OP_CFG_ADDR 0x1C1E
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#define MT6373_RG_LDO_VCN33_2_RC12_OP_CFG_ADDR 0x1C1E
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#define MT6373_RG_LDO_VCN33_2_RC13_OP_CFG_ADDR 0x1C1E
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#define MT6373_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_SW_OP_CFG_ADDR 0x1C1F
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#define MT6373_RG_LDO_VCN33_2_RC0_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC1_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC2_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC3_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC4_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC5_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC6_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC7_OP_MODE_ADDR 0x1C20
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#define MT6373_RG_LDO_VCN33_2_RC8_OP_MODE_ADDR 0x1C21
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#define MT6373_RG_LDO_VCN33_2_RC9_OP_MODE_ADDR 0x1C21
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#define MT6373_RG_LDO_VCN33_2_RC10_OP_MODE_ADDR 0x1C21
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#define MT6373_RG_LDO_VCN33_2_RC11_OP_MODE_ADDR 0x1C21
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#define MT6373_RG_LDO_VCN33_2_RC12_OP_MODE_ADDR 0x1C21
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#define MT6373_RG_LDO_VCN33_2_RC13_OP_MODE_ADDR 0x1C21
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#define MT6373_RG_LDO_VCN33_2_HW0_OP_MODE_ADDR 0x1C22
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#define MT6373_RG_LDO_VCN33_2_HW1_OP_MODE_ADDR 0x1C22
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#define MT6373_RG_LDO_VCN33_2_HW2_OP_MODE_ADDR 0x1C22
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#define MT6373_RG_LDO_VCN33_2_HW3_OP_MODE_ADDR 0x1C22
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#define MT6373_RG_LDO_VCN33_2_HW4_OP_MODE_ADDR 0x1C22
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#define MT6373_RG_LDO_VCN33_2_HW5_OP_MODE_ADDR 0x1C22
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#define MT6373_RG_LDO_VCN33_2_HW6_OP_MODE_ADDR 0x1C22
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#define MT6373_RG_LDO_VCN33_3_ONLV_EN_ADDR 0x1C24
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#define MT6373_RG_LDO_VCN33_3_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VCN33_3_RC0_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC1_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC2_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC3_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC4_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC5_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC6_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC7_OP_EN_ADDR 0x1C28
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#define MT6373_RG_LDO_VCN33_3_RC8_OP_EN_ADDR 0x1C29
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#define MT6373_RG_LDO_VCN33_3_RC9_OP_EN_ADDR 0x1C29
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#define MT6373_RG_LDO_VCN33_3_RC10_OP_EN_ADDR 0x1C29
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#define MT6373_RG_LDO_VCN33_3_RC11_OP_EN_ADDR 0x1C29
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#define MT6373_RG_LDO_VCN33_3_RC12_OP_EN_ADDR 0x1C29
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#define MT6373_RG_LDO_VCN33_3_RC13_OP_EN_ADDR 0x1C29
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#define MT6373_RG_LDO_VCN33_3_HW0_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_HW1_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_HW2_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_HW3_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_HW4_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_HW5_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_HW6_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_SW_OP_EN_ADDR 0x1C2A
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#define MT6373_RG_LDO_VCN33_3_RC0_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC1_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC2_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC3_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC4_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC5_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC6_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC7_OP_CFG_ADDR 0x1C2B
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#define MT6373_RG_LDO_VCN33_3_RC8_OP_CFG_ADDR 0x1C2C
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#define MT6373_RG_LDO_VCN33_3_RC9_OP_CFG_ADDR 0x1C2C
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#define MT6373_RG_LDO_VCN33_3_RC10_OP_CFG_ADDR 0x1C2C
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#define MT6373_RG_LDO_VCN33_3_RC11_OP_CFG_ADDR 0x1C2C
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#define MT6373_RG_LDO_VCN33_3_RC12_OP_CFG_ADDR 0x1C2C
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#define MT6373_RG_LDO_VCN33_3_RC13_OP_CFG_ADDR 0x1C2C
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#define MT6373_RG_LDO_VCN33_3_HW0_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_HW1_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_HW2_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_HW3_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_HW4_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_HW5_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_HW6_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_SW_OP_CFG_ADDR 0x1C2D
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#define MT6373_RG_LDO_VCN33_3_RC0_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC1_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC2_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC3_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC4_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC5_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC6_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC7_OP_MODE_ADDR 0x1C2E
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#define MT6373_RG_LDO_VCN33_3_RC8_OP_MODE_ADDR 0x1C2F
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#define MT6373_RG_LDO_VCN33_3_RC9_OP_MODE_ADDR 0x1C2F
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#define MT6373_RG_LDO_VCN33_3_RC10_OP_MODE_ADDR 0x1C2F
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#define MT6373_RG_LDO_VCN33_3_RC11_OP_MODE_ADDR 0x1C2F
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#define MT6373_RG_LDO_VCN33_3_RC12_OP_MODE_ADDR 0x1C2F
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#define MT6373_RG_LDO_VCN33_3_RC13_OP_MODE_ADDR 0x1C2F
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#define MT6373_RG_LDO_VCN33_3_HW0_OP_MODE_ADDR 0x1C30
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#define MT6373_RG_LDO_VCN33_3_HW1_OP_MODE_ADDR 0x1C30
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#define MT6373_RG_LDO_VCN33_3_HW2_OP_MODE_ADDR 0x1C30
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#define MT6373_RG_LDO_VCN33_3_HW3_OP_MODE_ADDR 0x1C30
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#define MT6373_RG_LDO_VCN33_3_HW4_OP_MODE_ADDR 0x1C30
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#define MT6373_RG_LDO_VCN33_3_HW5_OP_MODE_ADDR 0x1C30
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#define MT6373_RG_LDO_VCN33_3_HW6_OP_MODE_ADDR 0x1C30
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#define MT6373_RG_LDO_VCN18IO_ONLV_EN_ADDR 0x1C32
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#define MT6373_RG_LDO_VCN18IO_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VCN18IO_RC0_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC1_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC2_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC3_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC4_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC5_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC6_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC7_OP_EN_ADDR 0x1C36
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#define MT6373_RG_LDO_VCN18IO_RC8_OP_EN_ADDR 0x1C37
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#define MT6373_RG_LDO_VCN18IO_RC9_OP_EN_ADDR 0x1C37
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#define MT6373_RG_LDO_VCN18IO_RC10_OP_EN_ADDR 0x1C37
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#define MT6373_RG_LDO_VCN18IO_RC11_OP_EN_ADDR 0x1C37
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#define MT6373_RG_LDO_VCN18IO_RC12_OP_EN_ADDR 0x1C37
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#define MT6373_RG_LDO_VCN18IO_RC13_OP_EN_ADDR 0x1C37
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#define MT6373_RG_LDO_VCN18IO_HW0_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_HW1_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_HW2_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_HW3_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_HW4_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_HW5_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_HW6_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_SW_OP_EN_ADDR 0x1C38
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#define MT6373_RG_LDO_VCN18IO_RC0_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC1_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC2_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC3_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC4_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC5_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC6_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC7_OP_CFG_ADDR 0x1C39
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#define MT6373_RG_LDO_VCN18IO_RC8_OP_CFG_ADDR 0x1C3A
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#define MT6373_RG_LDO_VCN18IO_RC9_OP_CFG_ADDR 0x1C3A
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#define MT6373_RG_LDO_VCN18IO_RC10_OP_CFG_ADDR 0x1C3A
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#define MT6373_RG_LDO_VCN18IO_RC11_OP_CFG_ADDR 0x1C3A
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#define MT6373_RG_LDO_VCN18IO_RC12_OP_CFG_ADDR 0x1C3A
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#define MT6373_RG_LDO_VCN18IO_RC13_OP_CFG_ADDR 0x1C3A
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#define MT6373_RG_LDO_VCN18IO_HW0_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_HW1_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_HW2_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_HW3_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_HW4_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_HW5_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_HW6_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_SW_OP_CFG_ADDR 0x1C3B
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#define MT6373_RG_LDO_VCN18IO_RC0_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC1_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC2_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC3_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC4_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC5_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC6_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC7_OP_MODE_ADDR 0x1C3C
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#define MT6373_RG_LDO_VCN18IO_RC8_OP_MODE_ADDR 0x1C3D
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#define MT6373_RG_LDO_VCN18IO_RC9_OP_MODE_ADDR 0x1C3D
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#define MT6373_RG_LDO_VCN18IO_RC10_OP_MODE_ADDR 0x1C3D
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#define MT6373_RG_LDO_VCN18IO_RC11_OP_MODE_ADDR 0x1C3D
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#define MT6373_RG_LDO_VCN18IO_RC12_OP_MODE_ADDR 0x1C3D
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#define MT6373_RG_LDO_VCN18IO_RC13_OP_MODE_ADDR 0x1C3D
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#define MT6373_RG_LDO_VCN18IO_HW0_OP_MODE_ADDR 0x1C3E
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#define MT6373_RG_LDO_VCN18IO_HW1_OP_MODE_ADDR 0x1C3E
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#define MT6373_RG_LDO_VCN18IO_HW2_OP_MODE_ADDR 0x1C3E
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#define MT6373_RG_LDO_VCN18IO_HW3_OP_MODE_ADDR 0x1C3E
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#define MT6373_RG_LDO_VCN18IO_HW4_OP_MODE_ADDR 0x1C3E
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#define MT6373_RG_LDO_VCN18IO_HW5_OP_MODE_ADDR 0x1C3E
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#define MT6373_RG_LDO_VCN18IO_HW6_OP_MODE_ADDR 0x1C3E
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#define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_ADDR 0x1C40
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#define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_EN_ADDR 0x1C44
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#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_EN_ADDR 0x1C45
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#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_EN_ADDR 0x1C45
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#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_EN_ADDR 0x1C45
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#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_EN_ADDR 0x1C45
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#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_EN_ADDR 0x1C45
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#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_EN_ADDR 0x1C45
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#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_SW_OP_EN_ADDR 0x1C46
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#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_CFG_ADDR 0x1C47
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#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_CFG_ADDR 0x1C48
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#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_CFG_ADDR 0x1C48
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#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_CFG_ADDR 0x1C48
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#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_CFG_ADDR 0x1C48
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#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_CFG_ADDR 0x1C48
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#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_CFG_ADDR 0x1C48
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#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_SW_OP_CFG_ADDR 0x1C49
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#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_MODE_ADDR 0x1C4A
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#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_MODE_ADDR 0x1C4B
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#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_MODE_ADDR 0x1C4B
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#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_MODE_ADDR 0x1C4B
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#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_MODE_ADDR 0x1C4B
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#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_MODE_ADDR 0x1C4B
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#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_MODE_ADDR 0x1C4B
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#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_MODE_ADDR 0x1C4C
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#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_MODE_ADDR 0x1C4C
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#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_MODE_ADDR 0x1C4C
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#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_MODE_ADDR 0x1C4C
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#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_MODE_ADDR 0x1C4C
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#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_MODE_ADDR 0x1C4C
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#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_MODE_ADDR 0x1C4C
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#define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_ADDR 0x1C4E
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#define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_EN_ADDR 0x1C52
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#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_EN_ADDR 0x1C53
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#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_EN_ADDR 0x1C53
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#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_EN_ADDR 0x1C53
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#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_EN_ADDR 0x1C53
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#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_EN_ADDR 0x1C53
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#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_EN_ADDR 0x1C53
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#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_SW_OP_EN_ADDR 0x1C54
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#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_CFG_ADDR 0x1C55
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#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_CFG_ADDR 0x1C56
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#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_CFG_ADDR 0x1C56
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#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_CFG_ADDR 0x1C56
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#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_CFG_ADDR 0x1C56
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#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_CFG_ADDR 0x1C56
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#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_CFG_ADDR 0x1C56
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#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_SW_OP_CFG_ADDR 0x1C57
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#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_MODE_ADDR 0x1C58
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#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_MODE_ADDR 0x1C59
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#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_MODE_ADDR 0x1C59
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#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_MODE_ADDR 0x1C59
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#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_MODE_ADDR 0x1C59
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#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_MODE_ADDR 0x1C59
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#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_MODE_ADDR 0x1C59
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#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_MODE_ADDR 0x1C5A
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#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_MODE_ADDR 0x1C5A
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#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_MODE_ADDR 0x1C5A
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#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_MODE_ADDR 0x1C5A
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#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_MODE_ADDR 0x1C5A
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#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_MODE_ADDR 0x1C5A
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#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_MODE_ADDR 0x1C5A
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#define MT6373_RG_LDO_VANT18_ONLV_EN_ADDR 0x1C88
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#define MT6373_RG_LDO_VANT18_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VANT18_RC0_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC1_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC2_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC3_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC4_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC5_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC6_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC7_OP_EN_ADDR 0x1C8C
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#define MT6373_RG_LDO_VANT18_RC8_OP_EN_ADDR 0x1C8D
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#define MT6373_RG_LDO_VANT18_RC9_OP_EN_ADDR 0x1C8D
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#define MT6373_RG_LDO_VANT18_RC10_OP_EN_ADDR 0x1C8D
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#define MT6373_RG_LDO_VANT18_RC11_OP_EN_ADDR 0x1C8D
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#define MT6373_RG_LDO_VANT18_RC12_OP_EN_ADDR 0x1C8D
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#define MT6373_RG_LDO_VANT18_RC13_OP_EN_ADDR 0x1C8D
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#define MT6373_RG_LDO_VANT18_HW0_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_HW1_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_HW2_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_HW3_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_HW4_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_HW5_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_HW6_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_SW_OP_EN_ADDR 0x1C8E
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#define MT6373_RG_LDO_VANT18_RC0_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC1_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC2_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC3_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC4_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC5_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC6_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC7_OP_CFG_ADDR 0x1C8F
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#define MT6373_RG_LDO_VANT18_RC8_OP_CFG_ADDR 0x1C90
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#define MT6373_RG_LDO_VANT18_RC9_OP_CFG_ADDR 0x1C90
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#define MT6373_RG_LDO_VANT18_RC10_OP_CFG_ADDR 0x1C90
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#define MT6373_RG_LDO_VANT18_RC11_OP_CFG_ADDR 0x1C90
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#define MT6373_RG_LDO_VANT18_RC12_OP_CFG_ADDR 0x1C90
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#define MT6373_RG_LDO_VANT18_RC13_OP_CFG_ADDR 0x1C90
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#define MT6373_RG_LDO_VANT18_HW0_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_HW1_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_HW2_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_HW3_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_HW4_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_HW5_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_HW6_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_SW_OP_CFG_ADDR 0x1C91
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#define MT6373_RG_LDO_VANT18_RC0_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC1_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC2_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC3_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC4_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC5_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC6_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC7_OP_MODE_ADDR 0x1C92
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#define MT6373_RG_LDO_VANT18_RC8_OP_MODE_ADDR 0x1C93
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#define MT6373_RG_LDO_VANT18_RC9_OP_MODE_ADDR 0x1C93
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#define MT6373_RG_LDO_VANT18_RC10_OP_MODE_ADDR 0x1C93
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#define MT6373_RG_LDO_VANT18_RC11_OP_MODE_ADDR 0x1C93
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#define MT6373_RG_LDO_VANT18_RC12_OP_MODE_ADDR 0x1C93
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#define MT6373_RG_LDO_VANT18_RC13_OP_MODE_ADDR 0x1C93
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#define MT6373_RG_LDO_VANT18_HW0_OP_MODE_ADDR 0x1C94
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#define MT6373_RG_LDO_VANT18_HW1_OP_MODE_ADDR 0x1C94
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#define MT6373_RG_LDO_VANT18_HW2_OP_MODE_ADDR 0x1C94
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#define MT6373_RG_LDO_VANT18_HW3_OP_MODE_ADDR 0x1C94
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#define MT6373_RG_LDO_VANT18_HW4_OP_MODE_ADDR 0x1C94
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#define MT6373_RG_LDO_VANT18_HW5_OP_MODE_ADDR 0x1C94
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#define MT6373_RG_LDO_VANT18_HW6_OP_MODE_ADDR 0x1C94
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#define MT6373_RG_LDO_VMDDR_ONLV_EN_ADDR 0x1C96
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#define MT6373_RG_LDO_VMDDR_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VMDDR_RC0_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC1_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC2_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC3_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC4_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC5_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC6_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC7_OP_EN_ADDR 0x1C9A
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#define MT6373_RG_LDO_VMDDR_RC8_OP_EN_ADDR 0x1C9B
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#define MT6373_RG_LDO_VMDDR_RC9_OP_EN_ADDR 0x1C9B
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#define MT6373_RG_LDO_VMDDR_RC10_OP_EN_ADDR 0x1C9B
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#define MT6373_RG_LDO_VMDDR_RC11_OP_EN_ADDR 0x1C9B
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#define MT6373_RG_LDO_VMDDR_RC12_OP_EN_ADDR 0x1C9B
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#define MT6373_RG_LDO_VMDDR_RC13_OP_EN_ADDR 0x1C9B
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#define MT6373_RG_LDO_VMDDR_HW0_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_HW1_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_HW2_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_HW3_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_HW4_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_HW5_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_HW6_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_SW_OP_EN_ADDR 0x1C9C
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#define MT6373_RG_LDO_VMDDR_RC0_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC1_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC2_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC3_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC4_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC5_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC6_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC7_OP_CFG_ADDR 0x1C9D
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#define MT6373_RG_LDO_VMDDR_RC8_OP_CFG_ADDR 0x1C9E
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#define MT6373_RG_LDO_VMDDR_RC9_OP_CFG_ADDR 0x1C9E
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#define MT6373_RG_LDO_VMDDR_RC10_OP_CFG_ADDR 0x1C9E
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#define MT6373_RG_LDO_VMDDR_RC11_OP_CFG_ADDR 0x1C9E
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#define MT6373_RG_LDO_VMDDR_RC12_OP_CFG_ADDR 0x1C9E
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#define MT6373_RG_LDO_VMDDR_RC13_OP_CFG_ADDR 0x1C9E
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#define MT6373_RG_LDO_VMDDR_HW0_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_HW1_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_HW2_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_HW3_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_HW4_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_HW5_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_HW6_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_SW_OP_CFG_ADDR 0x1C9F
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#define MT6373_RG_LDO_VMDDR_RC0_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC1_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC2_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC3_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC4_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC5_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC6_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC7_OP_MODE_ADDR 0x1CA0
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#define MT6373_RG_LDO_VMDDR_RC8_OP_MODE_ADDR 0x1CA1
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#define MT6373_RG_LDO_VMDDR_RC9_OP_MODE_ADDR 0x1CA1
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#define MT6373_RG_LDO_VMDDR_RC10_OP_MODE_ADDR 0x1CA1
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#define MT6373_RG_LDO_VMDDR_RC11_OP_MODE_ADDR 0x1CA1
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#define MT6373_RG_LDO_VMDDR_RC12_OP_MODE_ADDR 0x1CA1
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#define MT6373_RG_LDO_VMDDR_RC13_OP_MODE_ADDR 0x1CA1
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#define MT6373_RG_LDO_VMDDR_HW0_OP_MODE_ADDR 0x1CA2
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#define MT6373_RG_LDO_VMDDR_HW1_OP_MODE_ADDR 0x1CA2
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#define MT6373_RG_LDO_VMDDR_HW2_OP_MODE_ADDR 0x1CA2
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#define MT6373_RG_LDO_VMDDR_HW3_OP_MODE_ADDR 0x1CA2
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#define MT6373_RG_LDO_VMDDR_HW4_OP_MODE_ADDR 0x1CA2
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#define MT6373_RG_LDO_VMDDR_HW5_OP_MODE_ADDR 0x1CA2
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#define MT6373_RG_LDO_VMDDR_HW6_OP_MODE_ADDR 0x1CA2
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#define MT6373_RG_LDO_VEFUSE_ONLV_EN_ADDR 0x1CA4
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#define MT6373_RG_LDO_VEFUSE_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VEFUSE_RC0_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC1_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC2_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC3_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC4_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC5_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC6_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC7_OP_EN_ADDR 0x1CA8
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#define MT6373_RG_LDO_VEFUSE_RC8_OP_EN_ADDR 0x1CA9
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#define MT6373_RG_LDO_VEFUSE_RC9_OP_EN_ADDR 0x1CA9
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#define MT6373_RG_LDO_VEFUSE_RC10_OP_EN_ADDR 0x1CA9
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#define MT6373_RG_LDO_VEFUSE_RC11_OP_EN_ADDR 0x1CA9
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#define MT6373_RG_LDO_VEFUSE_RC12_OP_EN_ADDR 0x1CA9
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#define MT6373_RG_LDO_VEFUSE_RC13_OP_EN_ADDR 0x1CA9
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#define MT6373_RG_LDO_VEFUSE_HW0_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_HW1_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_HW2_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_HW3_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_HW4_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_HW5_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_HW6_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_SW_OP_EN_ADDR 0x1CAA
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#define MT6373_RG_LDO_VEFUSE_RC0_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC1_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC2_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC3_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC4_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC5_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC6_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC7_OP_CFG_ADDR 0x1CAB
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#define MT6373_RG_LDO_VEFUSE_RC8_OP_CFG_ADDR 0x1CAC
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#define MT6373_RG_LDO_VEFUSE_RC9_OP_CFG_ADDR 0x1CAC
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#define MT6373_RG_LDO_VEFUSE_RC10_OP_CFG_ADDR 0x1CAC
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#define MT6373_RG_LDO_VEFUSE_RC11_OP_CFG_ADDR 0x1CAC
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#define MT6373_RG_LDO_VEFUSE_RC12_OP_CFG_ADDR 0x1CAC
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#define MT6373_RG_LDO_VEFUSE_RC13_OP_CFG_ADDR 0x1CAC
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#define MT6373_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_SW_OP_CFG_ADDR 0x1CAD
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#define MT6373_RG_LDO_VEFUSE_RC0_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC1_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC2_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC3_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC4_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC5_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC6_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC7_OP_MODE_ADDR 0x1CAE
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#define MT6373_RG_LDO_VEFUSE_RC8_OP_MODE_ADDR 0x1CAF
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#define MT6373_RG_LDO_VEFUSE_RC9_OP_MODE_ADDR 0x1CAF
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#define MT6373_RG_LDO_VEFUSE_RC10_OP_MODE_ADDR 0x1CAF
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#define MT6373_RG_LDO_VEFUSE_RC11_OP_MODE_ADDR 0x1CAF
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#define MT6373_RG_LDO_VEFUSE_RC12_OP_MODE_ADDR 0x1CAF
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#define MT6373_RG_LDO_VEFUSE_RC13_OP_MODE_ADDR 0x1CAF
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#define MT6373_RG_LDO_VEFUSE_HW0_OP_MODE_ADDR 0x1CB0
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#define MT6373_RG_LDO_VEFUSE_HW1_OP_MODE_ADDR 0x1CB0
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#define MT6373_RG_LDO_VEFUSE_HW2_OP_MODE_ADDR 0x1CB0
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#define MT6373_RG_LDO_VEFUSE_HW3_OP_MODE_ADDR 0x1CB0
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#define MT6373_RG_LDO_VEFUSE_HW4_OP_MODE_ADDR 0x1CB0
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#define MT6373_RG_LDO_VEFUSE_HW5_OP_MODE_ADDR 0x1CB0
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#define MT6373_RG_LDO_VEFUSE_HW6_OP_MODE_ADDR 0x1CB0
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#define MT6373_RG_LDO_VMCH_ONLV_EN_ADDR 0x1CB2
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#define MT6373_RG_LDO_VMCH_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VMCH_RC0_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC1_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC2_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC3_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC4_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC5_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC6_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC7_OP_EN_ADDR 0x1CB6
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#define MT6373_RG_LDO_VMCH_RC8_OP_EN_ADDR 0x1CB7
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#define MT6373_RG_LDO_VMCH_RC9_OP_EN_ADDR 0x1CB7
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#define MT6373_RG_LDO_VMCH_RC10_OP_EN_ADDR 0x1CB7
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#define MT6373_RG_LDO_VMCH_RC11_OP_EN_ADDR 0x1CB7
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#define MT6373_RG_LDO_VMCH_RC12_OP_EN_ADDR 0x1CB7
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#define MT6373_RG_LDO_VMCH_RC13_OP_EN_ADDR 0x1CB7
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#define MT6373_RG_LDO_VMCH_HW0_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_HW1_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_HW2_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_HW3_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_HW4_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_HW5_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_HW6_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_SW_OP_EN_ADDR 0x1CB8
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#define MT6373_RG_LDO_VMCH_RC0_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC1_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC2_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC3_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC4_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC5_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC6_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC7_OP_CFG_ADDR 0x1CB9
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#define MT6373_RG_LDO_VMCH_RC8_OP_CFG_ADDR 0x1CBA
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#define MT6373_RG_LDO_VMCH_RC9_OP_CFG_ADDR 0x1CBA
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#define MT6373_RG_LDO_VMCH_RC10_OP_CFG_ADDR 0x1CBA
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#define MT6373_RG_LDO_VMCH_RC11_OP_CFG_ADDR 0x1CBA
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#define MT6373_RG_LDO_VMCH_RC12_OP_CFG_ADDR 0x1CBA
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#define MT6373_RG_LDO_VMCH_RC13_OP_CFG_ADDR 0x1CBA
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#define MT6373_RG_LDO_VMCH_HW0_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_HW1_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_HW2_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_HW3_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_HW4_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_HW5_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_HW6_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_SW_OP_CFG_ADDR 0x1CBB
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#define MT6373_RG_LDO_VMCH_RC0_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC1_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC2_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC3_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC4_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC5_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC6_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC7_OP_MODE_ADDR 0x1CBC
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#define MT6373_RG_LDO_VMCH_RC8_OP_MODE_ADDR 0x1CBD
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#define MT6373_RG_LDO_VMCH_RC9_OP_MODE_ADDR 0x1CBD
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#define MT6373_RG_LDO_VMCH_RC10_OP_MODE_ADDR 0x1CBD
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#define MT6373_RG_LDO_VMCH_RC11_OP_MODE_ADDR 0x1CBD
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#define MT6373_RG_LDO_VMCH_RC12_OP_MODE_ADDR 0x1CBD
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#define MT6373_RG_LDO_VMCH_RC13_OP_MODE_ADDR 0x1CBD
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#define MT6373_RG_LDO_VMCH_HW0_OP_MODE_ADDR 0x1CBE
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#define MT6373_RG_LDO_VMCH_HW1_OP_MODE_ADDR 0x1CBE
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#define MT6373_RG_LDO_VMCH_HW2_OP_MODE_ADDR 0x1CBE
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#define MT6373_RG_LDO_VMCH_HW3_OP_MODE_ADDR 0x1CBE
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#define MT6373_RG_LDO_VMCH_HW4_OP_MODE_ADDR 0x1CBE
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#define MT6373_RG_LDO_VMCH_HW5_OP_MODE_ADDR 0x1CBE
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#define MT6373_RG_LDO_VMCH_HW6_OP_MODE_ADDR 0x1CBE
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#define MT6373_RG_LDO_VMC_ONLV_EN_ADDR 0x1CC1
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#define MT6373_RG_LDO_VMC_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VMC_RC0_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC1_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC2_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC3_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC4_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC5_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC6_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC7_OP_EN_ADDR 0x1CC5
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#define MT6373_RG_LDO_VMC_RC8_OP_EN_ADDR 0x1CC6
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#define MT6373_RG_LDO_VMC_RC9_OP_EN_ADDR 0x1CC6
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#define MT6373_RG_LDO_VMC_RC10_OP_EN_ADDR 0x1CC6
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#define MT6373_RG_LDO_VMC_RC11_OP_EN_ADDR 0x1CC6
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#define MT6373_RG_LDO_VMC_RC12_OP_EN_ADDR 0x1CC6
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#define MT6373_RG_LDO_VMC_RC13_OP_EN_ADDR 0x1CC6
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#define MT6373_RG_LDO_VMC_HW0_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_HW1_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_HW2_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_HW3_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_HW4_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_HW5_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_HW6_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_SW_OP_EN_ADDR 0x1CC7
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#define MT6373_RG_LDO_VMC_RC0_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC1_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC2_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC3_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC4_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC5_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC6_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC7_OP_CFG_ADDR 0x1CC8
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#define MT6373_RG_LDO_VMC_RC8_OP_CFG_ADDR 0x1CC9
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#define MT6373_RG_LDO_VMC_RC9_OP_CFG_ADDR 0x1CC9
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#define MT6373_RG_LDO_VMC_RC10_OP_CFG_ADDR 0x1CC9
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#define MT6373_RG_LDO_VMC_RC11_OP_CFG_ADDR 0x1CC9
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#define MT6373_RG_LDO_VMC_RC12_OP_CFG_ADDR 0x1CC9
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#define MT6373_RG_LDO_VMC_RC13_OP_CFG_ADDR 0x1CC9
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#define MT6373_RG_LDO_VMC_HW0_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_HW1_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_HW2_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_HW3_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_HW4_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_HW5_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_HW6_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_SW_OP_CFG_ADDR 0x1CCA
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#define MT6373_RG_LDO_VMC_RC0_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC1_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC2_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC3_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC4_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC5_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC6_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC7_OP_MODE_ADDR 0x1CCB
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#define MT6373_RG_LDO_VMC_RC8_OP_MODE_ADDR 0x1CCC
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#define MT6373_RG_LDO_VMC_RC9_OP_MODE_ADDR 0x1CCC
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#define MT6373_RG_LDO_VMC_RC10_OP_MODE_ADDR 0x1CCC
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#define MT6373_RG_LDO_VMC_RC11_OP_MODE_ADDR 0x1CCC
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#define MT6373_RG_LDO_VMC_RC12_OP_MODE_ADDR 0x1CCC
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#define MT6373_RG_LDO_VMC_RC13_OP_MODE_ADDR 0x1CCC
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#define MT6373_RG_LDO_VMC_HW0_OP_MODE_ADDR 0x1CCD
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#define MT6373_RG_LDO_VMC_HW1_OP_MODE_ADDR 0x1CCD
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#define MT6373_RG_LDO_VMC_HW2_OP_MODE_ADDR 0x1CCD
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#define MT6373_RG_LDO_VMC_HW3_OP_MODE_ADDR 0x1CCD
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#define MT6373_RG_LDO_VMC_HW4_OP_MODE_ADDR 0x1CCD
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#define MT6373_RG_LDO_VMC_HW5_OP_MODE_ADDR 0x1CCD
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#define MT6373_RG_LDO_VMC_HW6_OP_MODE_ADDR 0x1CCD
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#define MT6373_RG_LDO_VIBR_ONLV_EN_ADDR 0x1CCF
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#define MT6373_RG_LDO_VIBR_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VIBR_RC0_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC1_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC2_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC3_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC4_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC5_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC6_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC7_OP_EN_ADDR 0x1CD3
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#define MT6373_RG_LDO_VIBR_RC8_OP_EN_ADDR 0x1CD4
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#define MT6373_RG_LDO_VIBR_RC9_OP_EN_ADDR 0x1CD4
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#define MT6373_RG_LDO_VIBR_RC10_OP_EN_ADDR 0x1CD4
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#define MT6373_RG_LDO_VIBR_RC11_OP_EN_ADDR 0x1CD4
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#define MT6373_RG_LDO_VIBR_RC12_OP_EN_ADDR 0x1CD4
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#define MT6373_RG_LDO_VIBR_RC13_OP_EN_ADDR 0x1CD4
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#define MT6373_RG_LDO_VIBR_HW0_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_HW1_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_HW2_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_HW3_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_HW4_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_HW5_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_HW6_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_SW_OP_EN_ADDR 0x1CD5
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#define MT6373_RG_LDO_VIBR_RC0_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC1_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC2_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC3_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC4_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC5_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC6_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC7_OP_CFG_ADDR 0x1CD6
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#define MT6373_RG_LDO_VIBR_RC8_OP_CFG_ADDR 0x1CD7
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#define MT6373_RG_LDO_VIBR_RC9_OP_CFG_ADDR 0x1CD7
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#define MT6373_RG_LDO_VIBR_RC10_OP_CFG_ADDR 0x1CD7
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#define MT6373_RG_LDO_VIBR_RC11_OP_CFG_ADDR 0x1CD7
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#define MT6373_RG_LDO_VIBR_RC12_OP_CFG_ADDR 0x1CD7
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#define MT6373_RG_LDO_VIBR_RC13_OP_CFG_ADDR 0x1CD7
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#define MT6373_RG_LDO_VIBR_HW0_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_HW1_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_HW2_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_HW3_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_HW4_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_HW5_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_HW6_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_SW_OP_CFG_ADDR 0x1CD8
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#define MT6373_RG_LDO_VIBR_RC0_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC1_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC2_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC3_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC4_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC5_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC6_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC7_OP_MODE_ADDR 0x1CD9
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#define MT6373_RG_LDO_VIBR_RC8_OP_MODE_ADDR 0x1CDA
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#define MT6373_RG_LDO_VIBR_RC9_OP_MODE_ADDR 0x1CDA
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#define MT6373_RG_LDO_VIBR_RC10_OP_MODE_ADDR 0x1CDA
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#define MT6373_RG_LDO_VIBR_RC11_OP_MODE_ADDR 0x1CDA
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#define MT6373_RG_LDO_VIBR_RC12_OP_MODE_ADDR 0x1CDA
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#define MT6373_RG_LDO_VIBR_RC13_OP_MODE_ADDR 0x1CDA
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#define MT6373_RG_LDO_VIBR_HW0_OP_MODE_ADDR 0x1CDB
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#define MT6373_RG_LDO_VIBR_HW1_OP_MODE_ADDR 0x1CDB
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#define MT6373_RG_LDO_VIBR_HW2_OP_MODE_ADDR 0x1CDB
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#define MT6373_RG_LDO_VIBR_HW3_OP_MODE_ADDR 0x1CDB
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#define MT6373_RG_LDO_VIBR_HW4_OP_MODE_ADDR 0x1CDB
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#define MT6373_RG_LDO_VIBR_HW5_OP_MODE_ADDR 0x1CDB
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#define MT6373_RG_LDO_VIBR_HW6_OP_MODE_ADDR 0x1CDB
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#define MT6373_RG_LDO_VIO28_ONLV_EN_ADDR 0x1D08
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#define MT6373_RG_LDO_VIO28_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VIO28_RC0_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC1_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC2_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC3_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC4_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC5_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC6_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC7_OP_EN_ADDR 0x1D0C
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#define MT6373_RG_LDO_VIO28_RC8_OP_EN_ADDR 0x1D0D
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#define MT6373_RG_LDO_VIO28_RC9_OP_EN_ADDR 0x1D0D
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#define MT6373_RG_LDO_VIO28_RC10_OP_EN_ADDR 0x1D0D
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#define MT6373_RG_LDO_VIO28_RC11_OP_EN_ADDR 0x1D0D
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#define MT6373_RG_LDO_VIO28_RC12_OP_EN_ADDR 0x1D0D
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#define MT6373_RG_LDO_VIO28_RC13_OP_EN_ADDR 0x1D0D
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#define MT6373_RG_LDO_VIO28_HW0_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_HW1_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_HW2_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_HW3_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_HW4_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_HW5_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_HW6_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_SW_OP_EN_ADDR 0x1D0E
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#define MT6373_RG_LDO_VIO28_RC0_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC1_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC2_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC3_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC4_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC5_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC6_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC7_OP_CFG_ADDR 0x1D0F
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#define MT6373_RG_LDO_VIO28_RC8_OP_CFG_ADDR 0x1D10
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#define MT6373_RG_LDO_VIO28_RC9_OP_CFG_ADDR 0x1D10
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#define MT6373_RG_LDO_VIO28_RC10_OP_CFG_ADDR 0x1D10
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#define MT6373_RG_LDO_VIO28_RC11_OP_CFG_ADDR 0x1D10
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#define MT6373_RG_LDO_VIO28_RC12_OP_CFG_ADDR 0x1D10
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#define MT6373_RG_LDO_VIO28_RC13_OP_CFG_ADDR 0x1D10
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#define MT6373_RG_LDO_VIO28_HW0_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_HW1_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_HW2_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_HW3_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_HW4_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_HW5_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_HW6_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_SW_OP_CFG_ADDR 0x1D11
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#define MT6373_RG_LDO_VIO28_RC0_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC1_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC2_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC3_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC4_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC5_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC6_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC7_OP_MODE_ADDR 0x1D12
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#define MT6373_RG_LDO_VIO28_RC8_OP_MODE_ADDR 0x1D13
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#define MT6373_RG_LDO_VIO28_RC9_OP_MODE_ADDR 0x1D13
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#define MT6373_RG_LDO_VIO28_RC10_OP_MODE_ADDR 0x1D13
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#define MT6373_RG_LDO_VIO28_RC11_OP_MODE_ADDR 0x1D13
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#define MT6373_RG_LDO_VIO28_RC12_OP_MODE_ADDR 0x1D13
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#define MT6373_RG_LDO_VIO28_RC13_OP_MODE_ADDR 0x1D13
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#define MT6373_RG_LDO_VIO28_HW0_OP_MODE_ADDR 0x1D14
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#define MT6373_RG_LDO_VIO28_HW1_OP_MODE_ADDR 0x1D14
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#define MT6373_RG_LDO_VIO28_HW2_OP_MODE_ADDR 0x1D14
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#define MT6373_RG_LDO_VIO28_HW3_OP_MODE_ADDR 0x1D14
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#define MT6373_RG_LDO_VIO28_HW4_OP_MODE_ADDR 0x1D14
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#define MT6373_RG_LDO_VIO28_HW5_OP_MODE_ADDR 0x1D14
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#define MT6373_RG_LDO_VIO28_HW6_OP_MODE_ADDR 0x1D14
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#define MT6373_RG_LDO_VFP_ONLV_EN_ADDR 0x1D16
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#define MT6373_RG_LDO_VFP_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VFP_RC0_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC1_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC2_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC3_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC4_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC5_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC6_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC7_OP_EN_ADDR 0x1D1A
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#define MT6373_RG_LDO_VFP_RC8_OP_EN_ADDR 0x1D1B
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#define MT6373_RG_LDO_VFP_RC9_OP_EN_ADDR 0x1D1B
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#define MT6373_RG_LDO_VFP_RC10_OP_EN_ADDR 0x1D1B
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#define MT6373_RG_LDO_VFP_RC11_OP_EN_ADDR 0x1D1B
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#define MT6373_RG_LDO_VFP_RC12_OP_EN_ADDR 0x1D1B
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#define MT6373_RG_LDO_VFP_RC13_OP_EN_ADDR 0x1D1B
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#define MT6373_RG_LDO_VFP_HW0_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_HW1_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_HW2_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_HW3_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_HW4_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_HW5_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_HW6_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_SW_OP_EN_ADDR 0x1D1C
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#define MT6373_RG_LDO_VFP_RC0_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC1_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC2_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC3_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC4_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC5_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC6_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC7_OP_CFG_ADDR 0x1D1D
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#define MT6373_RG_LDO_VFP_RC8_OP_CFG_ADDR 0x1D1E
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#define MT6373_RG_LDO_VFP_RC9_OP_CFG_ADDR 0x1D1E
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#define MT6373_RG_LDO_VFP_RC10_OP_CFG_ADDR 0x1D1E
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#define MT6373_RG_LDO_VFP_RC11_OP_CFG_ADDR 0x1D1E
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#define MT6373_RG_LDO_VFP_RC12_OP_CFG_ADDR 0x1D1E
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#define MT6373_RG_LDO_VFP_RC13_OP_CFG_ADDR 0x1D1E
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#define MT6373_RG_LDO_VFP_HW0_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_HW1_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_HW2_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_HW3_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_HW4_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_HW5_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_HW6_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_SW_OP_CFG_ADDR 0x1D1F
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#define MT6373_RG_LDO_VFP_RC0_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC1_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC2_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC3_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC4_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC5_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC6_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC7_OP_MODE_ADDR 0x1D20
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#define MT6373_RG_LDO_VFP_RC8_OP_MODE_ADDR 0x1D21
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#define MT6373_RG_LDO_VFP_RC9_OP_MODE_ADDR 0x1D21
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#define MT6373_RG_LDO_VFP_RC10_OP_MODE_ADDR 0x1D21
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#define MT6373_RG_LDO_VFP_RC11_OP_MODE_ADDR 0x1D21
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#define MT6373_RG_LDO_VFP_RC12_OP_MODE_ADDR 0x1D21
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#define MT6373_RG_LDO_VFP_RC13_OP_MODE_ADDR 0x1D21
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#define MT6373_RG_LDO_VFP_HW0_OP_MODE_ADDR 0x1D22
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#define MT6373_RG_LDO_VFP_HW1_OP_MODE_ADDR 0x1D22
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#define MT6373_RG_LDO_VFP_HW2_OP_MODE_ADDR 0x1D22
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#define MT6373_RG_LDO_VFP_HW3_OP_MODE_ADDR 0x1D22
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#define MT6373_RG_LDO_VFP_HW4_OP_MODE_ADDR 0x1D22
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#define MT6373_RG_LDO_VFP_HW5_OP_MODE_ADDR 0x1D22
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#define MT6373_RG_LDO_VFP_HW6_OP_MODE_ADDR 0x1D22
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#define MT6373_RG_LDO_VTP_ONLV_EN_ADDR 0x1D24
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#define MT6373_RG_LDO_VTP_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VTP_RC0_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC1_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC2_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC3_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC4_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC5_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC6_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC7_OP_EN_ADDR 0x1D28
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#define MT6373_RG_LDO_VTP_RC8_OP_EN_ADDR 0x1D29
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#define MT6373_RG_LDO_VTP_RC9_OP_EN_ADDR 0x1D29
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#define MT6373_RG_LDO_VTP_RC10_OP_EN_ADDR 0x1D29
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#define MT6373_RG_LDO_VTP_RC11_OP_EN_ADDR 0x1D29
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#define MT6373_RG_LDO_VTP_RC12_OP_EN_ADDR 0x1D29
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#define MT6373_RG_LDO_VTP_RC13_OP_EN_ADDR 0x1D29
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#define MT6373_RG_LDO_VTP_HW0_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_HW1_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_HW2_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_HW3_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_HW4_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_HW5_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_HW6_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_SW_OP_EN_ADDR 0x1D2A
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#define MT6373_RG_LDO_VTP_RC0_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC1_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC2_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC3_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC4_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC5_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC6_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC7_OP_CFG_ADDR 0x1D2B
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#define MT6373_RG_LDO_VTP_RC8_OP_CFG_ADDR 0x1D2C
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#define MT6373_RG_LDO_VTP_RC9_OP_CFG_ADDR 0x1D2C
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#define MT6373_RG_LDO_VTP_RC10_OP_CFG_ADDR 0x1D2C
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#define MT6373_RG_LDO_VTP_RC11_OP_CFG_ADDR 0x1D2C
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#define MT6373_RG_LDO_VTP_RC12_OP_CFG_ADDR 0x1D2C
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#define MT6373_RG_LDO_VTP_RC13_OP_CFG_ADDR 0x1D2C
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#define MT6373_RG_LDO_VTP_HW0_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_HW1_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_HW2_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_HW3_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_HW4_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_HW5_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_HW6_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_SW_OP_CFG_ADDR 0x1D2D
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#define MT6373_RG_LDO_VTP_RC0_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC1_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC2_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC3_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC4_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC5_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC6_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC7_OP_MODE_ADDR 0x1D2E
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#define MT6373_RG_LDO_VTP_RC8_OP_MODE_ADDR 0x1D2F
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#define MT6373_RG_LDO_VTP_RC9_OP_MODE_ADDR 0x1D2F
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#define MT6373_RG_LDO_VTP_RC10_OP_MODE_ADDR 0x1D2F
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#define MT6373_RG_LDO_VTP_RC11_OP_MODE_ADDR 0x1D2F
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#define MT6373_RG_LDO_VTP_RC12_OP_MODE_ADDR 0x1D2F
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#define MT6373_RG_LDO_VTP_RC13_OP_MODE_ADDR 0x1D2F
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#define MT6373_RG_LDO_VTP_HW0_OP_MODE_ADDR 0x1D30
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#define MT6373_RG_LDO_VTP_HW1_OP_MODE_ADDR 0x1D30
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#define MT6373_RG_LDO_VTP_HW2_OP_MODE_ADDR 0x1D30
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#define MT6373_RG_LDO_VTP_HW3_OP_MODE_ADDR 0x1D30
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#define MT6373_RG_LDO_VTP_HW4_OP_MODE_ADDR 0x1D30
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#define MT6373_RG_LDO_VTP_HW5_OP_MODE_ADDR 0x1D30
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#define MT6373_RG_LDO_VTP_HW6_OP_MODE_ADDR 0x1D30
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#define MT6373_RG_LDO_VSIM1_ONLV_EN_ADDR 0x1D32
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#define MT6373_RG_LDO_VSIM1_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VSIM1_RC0_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC1_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC2_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC3_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC4_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC5_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC6_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC7_OP_EN_ADDR 0x1D36
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#define MT6373_RG_LDO_VSIM1_RC8_OP_EN_ADDR 0x1D37
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#define MT6373_RG_LDO_VSIM1_RC9_OP_EN_ADDR 0x1D37
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#define MT6373_RG_LDO_VSIM1_RC10_OP_EN_ADDR 0x1D37
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#define MT6373_RG_LDO_VSIM1_RC11_OP_EN_ADDR 0x1D37
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#define MT6373_RG_LDO_VSIM1_RC12_OP_EN_ADDR 0x1D37
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#define MT6373_RG_LDO_VSIM1_RC13_OP_EN_ADDR 0x1D37
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#define MT6373_RG_LDO_VSIM1_HW0_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_HW1_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_HW2_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_HW3_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_HW4_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_HW5_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_HW6_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_SW_OP_EN_ADDR 0x1D38
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#define MT6373_RG_LDO_VSIM1_RC0_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC1_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC2_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC3_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC4_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC5_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC6_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC7_OP_CFG_ADDR 0x1D39
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#define MT6373_RG_LDO_VSIM1_RC8_OP_CFG_ADDR 0x1D3A
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#define MT6373_RG_LDO_VSIM1_RC9_OP_CFG_ADDR 0x1D3A
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#define MT6373_RG_LDO_VSIM1_RC10_OP_CFG_ADDR 0x1D3A
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#define MT6373_RG_LDO_VSIM1_RC11_OP_CFG_ADDR 0x1D3A
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#define MT6373_RG_LDO_VSIM1_RC12_OP_CFG_ADDR 0x1D3A
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#define MT6373_RG_LDO_VSIM1_RC13_OP_CFG_ADDR 0x1D3A
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#define MT6373_RG_LDO_VSIM1_HW0_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_HW1_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_HW2_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_HW3_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_HW4_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_HW5_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_HW6_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_SW_OP_CFG_ADDR 0x1D3B
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#define MT6373_RG_LDO_VSIM1_RC0_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC1_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC2_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC3_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC4_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC5_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC6_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC7_OP_MODE_ADDR 0x1D3C
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#define MT6373_RG_LDO_VSIM1_RC8_OP_MODE_ADDR 0x1D3D
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#define MT6373_RG_LDO_VSIM1_RC9_OP_MODE_ADDR 0x1D3D
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#define MT6373_RG_LDO_VSIM1_RC10_OP_MODE_ADDR 0x1D3D
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#define MT6373_RG_LDO_VSIM1_RC11_OP_MODE_ADDR 0x1D3D
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#define MT6373_RG_LDO_VSIM1_RC12_OP_MODE_ADDR 0x1D3D
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#define MT6373_RG_LDO_VSIM1_RC13_OP_MODE_ADDR 0x1D3D
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#define MT6373_RG_LDO_VSIM1_HW0_OP_MODE_ADDR 0x1D3E
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#define MT6373_RG_LDO_VSIM1_HW1_OP_MODE_ADDR 0x1D3E
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#define MT6373_RG_LDO_VSIM1_HW2_OP_MODE_ADDR 0x1D3E
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#define MT6373_RG_LDO_VSIM1_HW3_OP_MODE_ADDR 0x1D3E
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#define MT6373_RG_LDO_VSIM1_HW4_OP_MODE_ADDR 0x1D3E
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#define MT6373_RG_LDO_VSIM1_HW5_OP_MODE_ADDR 0x1D3E
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#define MT6373_RG_LDO_VSIM1_HW6_OP_MODE_ADDR 0x1D3E
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#define MT6373_RG_LDO_VSIM2_ONLV_EN_ADDR 0x1D41
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#define MT6373_RG_LDO_VSIM2_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VSIM2_RC0_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC1_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC2_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC3_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC4_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC5_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC6_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC7_OP_EN_ADDR 0x1D45
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#define MT6373_RG_LDO_VSIM2_RC8_OP_EN_ADDR 0x1D46
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#define MT6373_RG_LDO_VSIM2_RC9_OP_EN_ADDR 0x1D46
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#define MT6373_RG_LDO_VSIM2_RC10_OP_EN_ADDR 0x1D46
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#define MT6373_RG_LDO_VSIM2_RC11_OP_EN_ADDR 0x1D46
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#define MT6373_RG_LDO_VSIM2_RC12_OP_EN_ADDR 0x1D46
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#define MT6373_RG_LDO_VSIM2_RC13_OP_EN_ADDR 0x1D46
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#define MT6373_RG_LDO_VSIM2_HW0_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_HW1_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_HW2_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_HW3_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_HW4_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_HW5_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_HW6_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_SW_OP_EN_ADDR 0x1D47
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#define MT6373_RG_LDO_VSIM2_RC0_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC1_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC2_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC3_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC4_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC5_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC6_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC7_OP_CFG_ADDR 0x1D48
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#define MT6373_RG_LDO_VSIM2_RC8_OP_CFG_ADDR 0x1D49
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#define MT6373_RG_LDO_VSIM2_RC9_OP_CFG_ADDR 0x1D49
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#define MT6373_RG_LDO_VSIM2_RC10_OP_CFG_ADDR 0x1D49
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#define MT6373_RG_LDO_VSIM2_RC11_OP_CFG_ADDR 0x1D49
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#define MT6373_RG_LDO_VSIM2_RC12_OP_CFG_ADDR 0x1D49
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#define MT6373_RG_LDO_VSIM2_RC13_OP_CFG_ADDR 0x1D49
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#define MT6373_RG_LDO_VSIM2_HW0_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_HW1_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_HW2_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_HW3_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_HW4_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_HW5_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_HW6_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_SW_OP_CFG_ADDR 0x1D4A
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#define MT6373_RG_LDO_VSIM2_RC0_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC1_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC2_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC3_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC4_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC5_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC6_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC7_OP_MODE_ADDR 0x1D4B
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#define MT6373_RG_LDO_VSIM2_RC8_OP_MODE_ADDR 0x1D4C
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#define MT6373_RG_LDO_VSIM2_RC9_OP_MODE_ADDR 0x1D4C
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#define MT6373_RG_LDO_VSIM2_RC10_OP_MODE_ADDR 0x1D4C
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#define MT6373_RG_LDO_VSIM2_RC11_OP_MODE_ADDR 0x1D4C
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#define MT6373_RG_LDO_VSIM2_RC12_OP_MODE_ADDR 0x1D4C
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#define MT6373_RG_LDO_VSIM2_RC13_OP_MODE_ADDR 0x1D4C
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#define MT6373_RG_LDO_VSIM2_HW0_OP_MODE_ADDR 0x1D4D
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#define MT6373_RG_LDO_VSIM2_HW1_OP_MODE_ADDR 0x1D4D
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#define MT6373_RG_LDO_VSIM2_HW2_OP_MODE_ADDR 0x1D4D
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#define MT6373_RG_LDO_VSIM2_HW3_OP_MODE_ADDR 0x1D4D
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#define MT6373_RG_LDO_VSIM2_HW4_OP_MODE_ADDR 0x1D4D
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#define MT6373_RG_LDO_VSIM2_HW5_OP_MODE_ADDR 0x1D4D
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#define MT6373_RG_LDO_VSIM2_HW6_OP_MODE_ADDR 0x1D4D
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_ADDR 0x1D88
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_SHIFT 3
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_VOSEL_SLEEP_ADDR 0x1D8D
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_EN_ADDR 0x1D94
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_EN_ADDR 0x1D95
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_EN_ADDR 0x1D95
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_EN_ADDR 0x1D95
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_EN_ADDR 0x1D95
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_EN_ADDR 0x1D95
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_EN_ADDR 0x1D95
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_EN_ADDR 0x1D96
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_CFG_ADDR 0x1D97
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_CFG_ADDR 0x1D98
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_CFG_ADDR 0x1D98
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_CFG_ADDR 0x1D98
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_CFG_ADDR 0x1D98
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_CFG_ADDR 0x1D98
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_CFG_ADDR 0x1D98
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_CFG_ADDR 0x1D99
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_MODE_ADDR 0x1D9A
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_MODE_ADDR 0x1D9B
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_MODE_ADDR 0x1D9B
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_MODE_ADDR 0x1D9B
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_MODE_ADDR 0x1D9B
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_MODE_ADDR 0x1D9B
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_MODE_ADDR 0x1D9B
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_MODE_ADDR 0x1D9C
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_MODE_ADDR 0x1D9C
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_MODE_ADDR 0x1D9C
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_MODE_ADDR 0x1D9C
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_MODE_ADDR 0x1D9C
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_MODE_ADDR 0x1D9C
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#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_MODE_ADDR 0x1D9C
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#endif /* MT6373_LOWPOWER_REG_H */
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