mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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d4e6f98d7f
1. Add PMIC shutdown API 2. Add PMIC low power settings Change-Id: I634a60fa3e2a74a6031df9fe59e2f52956ef7114 Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
2320 lines
121 KiB
C
2320 lines
121 KiB
C
/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT6363_LOWPOWER_REG_H
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#define MT6363_LOWPOWER_REG_H
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#define MT6363_RG_BUCK_VS2_VOSEL_SLEEP_ADDR 0x1487
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#define MT6363_RG_BUCK_VS2_ONLV_EN_ADDR 0x1488
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#define MT6363_RG_BUCK_VS2_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VS2_RC0_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC1_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC2_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC3_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC4_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC5_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC6_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC7_OP_EN_ADDR 0x148D
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#define MT6363_RG_BUCK_VS2_RC8_OP_EN_ADDR 0x148E
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#define MT6363_RG_BUCK_VS2_RC9_OP_EN_ADDR 0x148E
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#define MT6363_RG_BUCK_VS2_RC10_OP_EN_ADDR 0x148E
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#define MT6363_RG_BUCK_VS2_RC11_OP_EN_ADDR 0x148E
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#define MT6363_RG_BUCK_VS2_RC12_OP_EN_ADDR 0x148E
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#define MT6363_RG_BUCK_VS2_RC13_OP_EN_ADDR 0x148E
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#define MT6363_RG_BUCK_VS2_HW0_OP_EN_ADDR 0x148F
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#define MT6363_RG_BUCK_VS2_HW1_OP_EN_ADDR 0x148F
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#define MT6363_RG_BUCK_VS2_HW2_OP_EN_ADDR 0x148F
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#define MT6363_RG_BUCK_VS2_HW3_OP_EN_ADDR 0x148F
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#define MT6363_RG_BUCK_VS2_HW4_OP_EN_ADDR 0x148F
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#define MT6363_RG_BUCK_VS2_SW_OP_EN_ADDR 0x148F
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#define MT6363_RG_BUCK_VS2_RC0_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC1_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC2_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC3_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC4_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC5_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC6_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC7_OP_CFG_ADDR 0x1490
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#define MT6363_RG_BUCK_VS2_RC8_OP_CFG_ADDR 0x1491
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#define MT6363_RG_BUCK_VS2_RC9_OP_CFG_ADDR 0x1491
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#define MT6363_RG_BUCK_VS2_RC10_OP_CFG_ADDR 0x1491
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#define MT6363_RG_BUCK_VS2_RC11_OP_CFG_ADDR 0x1491
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#define MT6363_RG_BUCK_VS2_RC12_OP_CFG_ADDR 0x1491
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#define MT6363_RG_BUCK_VS2_RC13_OP_CFG_ADDR 0x1491
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#define MT6363_RG_BUCK_VS2_HW0_OP_CFG_ADDR 0x1492
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#define MT6363_RG_BUCK_VS2_HW1_OP_CFG_ADDR 0x1492
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#define MT6363_RG_BUCK_VS2_HW2_OP_CFG_ADDR 0x1492
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#define MT6363_RG_BUCK_VS2_HW3_OP_CFG_ADDR 0x1492
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#define MT6363_RG_BUCK_VS2_HW4_OP_CFG_ADDR 0x1492
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#define MT6363_RG_BUCK_VS2_RC0_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC1_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC2_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC3_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC4_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC5_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC6_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC7_OP_MODE_ADDR 0x1493
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#define MT6363_RG_BUCK_VS2_RC8_OP_MODE_ADDR 0x1494
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#define MT6363_RG_BUCK_VS2_RC9_OP_MODE_ADDR 0x1494
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#define MT6363_RG_BUCK_VS2_RC10_OP_MODE_ADDR 0x1494
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#define MT6363_RG_BUCK_VS2_RC11_OP_MODE_ADDR 0x1494
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#define MT6363_RG_BUCK_VS2_RC12_OP_MODE_ADDR 0x1494
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#define MT6363_RG_BUCK_VS2_RC13_OP_MODE_ADDR 0x1494
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#define MT6363_RG_BUCK_VS2_HW0_OP_MODE_ADDR 0x1495
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#define MT6363_RG_BUCK_VS2_HW1_OP_MODE_ADDR 0x1495
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#define MT6363_RG_BUCK_VS2_HW2_OP_MODE_ADDR 0x1495
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#define MT6363_RG_BUCK_VS2_HW3_OP_MODE_ADDR 0x1495
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#define MT6363_RG_BUCK_VS2_HW4_OP_MODE_ADDR 0x1495
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#define MT6363_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR 0x1507
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#define MT6363_RG_BUCK_VBUCK1_ONLV_EN_ADDR 0x1508
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#define MT6363_RG_BUCK_VBUCK1_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR 0x150D
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#define MT6363_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR 0x150E
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#define MT6363_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR 0x150E
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#define MT6363_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR 0x150E
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#define MT6363_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR 0x150E
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#define MT6363_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR 0x150E
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#define MT6363_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR 0x150E
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#define MT6363_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x150F
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#define MT6363_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x150F
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#define MT6363_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x150F
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#define MT6363_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x150F
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#define MT6363_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x150F
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#define MT6363_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR 0x1510
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#define MT6363_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR 0x1511
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#define MT6363_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR 0x1511
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#define MT6363_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR 0x1511
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#define MT6363_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR 0x1511
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#define MT6363_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR 0x1511
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#define MT6363_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR 0x1511
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#define MT6363_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1512
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#define MT6363_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1512
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#define MT6363_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1512
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#define MT6363_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1512
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#define MT6363_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR 0x1512
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#define MT6363_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR 0x1513
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#define MT6363_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR 0x1514
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#define MT6363_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR 0x1514
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#define MT6363_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR 0x1514
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#define MT6363_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR 0x1514
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#define MT6363_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR 0x1514
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#define MT6363_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR 0x1514
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#define MT6363_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1515
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#define MT6363_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1515
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#define MT6363_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1515
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#define MT6363_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1515
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#define MT6363_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR 0x1587
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#define MT6363_RG_BUCK_VBUCK2_ONLV_EN_ADDR 0x1588
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#define MT6363_RG_BUCK_VBUCK2_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR 0x158D
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#define MT6363_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR 0x158E
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#define MT6363_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR 0x158E
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#define MT6363_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR 0x158E
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#define MT6363_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR 0x158E
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#define MT6363_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR 0x158E
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#define MT6363_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR 0x158E
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#define MT6363_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x158F
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#define MT6363_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x158F
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#define MT6363_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x158F
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#define MT6363_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x158F
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#define MT6363_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x158F
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#define MT6363_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR 0x1590
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#define MT6363_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR 0x1591
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#define MT6363_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR 0x1591
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#define MT6363_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR 0x1591
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#define MT6363_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR 0x1591
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#define MT6363_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR 0x1591
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#define MT6363_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR 0x1591
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#define MT6363_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1592
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#define MT6363_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1592
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#define MT6363_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1592
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#define MT6363_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1592
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#define MT6363_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR 0x1593
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#define MT6363_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR 0x1594
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#define MT6363_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR 0x1594
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#define MT6363_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR 0x1594
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#define MT6363_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR 0x1594
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#define MT6363_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR 0x1594
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#define MT6363_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR 0x1594
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#define MT6363_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1595
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#define MT6363_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1595
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#define MT6363_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1595
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#define MT6363_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1595
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#define MT6363_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR 0x1607
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#define MT6363_RG_BUCK_VBUCK3_ONLV_EN_ADDR 0x1608
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#define MT6363_RG_BUCK_VBUCK3_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR 0x160D
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#define MT6363_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR 0x160E
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#define MT6363_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR 0x160E
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#define MT6363_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR 0x160E
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#define MT6363_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR 0x160E
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#define MT6363_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR 0x160E
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#define MT6363_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR 0x160E
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#define MT6363_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x160F
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#define MT6363_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x160F
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#define MT6363_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x160F
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#define MT6363_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x160F
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#define MT6363_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x160F
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#define MT6363_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR 0x1610
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#define MT6363_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR 0x1611
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#define MT6363_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR 0x1611
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#define MT6363_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR 0x1611
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#define MT6363_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR 0x1611
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#define MT6363_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR 0x1611
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#define MT6363_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR 0x1611
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#define MT6363_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1612
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#define MT6363_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1612
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#define MT6363_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1612
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#define MT6363_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1612
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#define MT6363_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR 0x1613
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#define MT6363_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR 0x1614
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#define MT6363_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR 0x1614
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#define MT6363_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR 0x1614
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#define MT6363_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR 0x1614
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#define MT6363_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR 0x1614
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#define MT6363_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR 0x1614
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#define MT6363_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1615
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#define MT6363_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1615
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#define MT6363_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1615
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#define MT6363_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1615
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#define MT6363_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR 0x1687
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#define MT6363_RG_BUCK_VBUCK4_ONLV_EN_ADDR 0x1688
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#define MT6363_RG_BUCK_VBUCK4_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR 0x168D
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#define MT6363_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR 0x168E
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#define MT6363_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR 0x168E
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#define MT6363_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR 0x168E
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#define MT6363_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR 0x168E
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#define MT6363_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR 0x168E
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#define MT6363_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR 0x168E
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#define MT6363_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x168F
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#define MT6363_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x168F
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#define MT6363_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x168F
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#define MT6363_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x168F
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#define MT6363_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x168F
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#define MT6363_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR 0x1690
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#define MT6363_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR 0x1691
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#define MT6363_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR 0x1691
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#define MT6363_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR 0x1691
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#define MT6363_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR 0x1691
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#define MT6363_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR 0x1691
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#define MT6363_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR 0x1691
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#define MT6363_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1692
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#define MT6363_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1692
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#define MT6363_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1692
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#define MT6363_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1692
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#define MT6363_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR 0x1693
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#define MT6363_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR 0x1694
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#define MT6363_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR 0x1694
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#define MT6363_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR 0x1694
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#define MT6363_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR 0x1694
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#define MT6363_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR 0x1694
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#define MT6363_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR 0x1694
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#define MT6363_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1695
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#define MT6363_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1695
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#define MT6363_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1695
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#define MT6363_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1695
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#define MT6363_RG_BUCK_VBUCK5_VOSEL_SLEEP_ADDR 0x1707
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#define MT6363_RG_BUCK_VBUCK5_ONLV_EN_ADDR 0x1708
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#define MT6363_RG_BUCK_VBUCK5_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VBUCK5_RC0_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC1_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC2_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC3_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC4_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC5_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC6_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC7_OP_EN_ADDR 0x170D
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#define MT6363_RG_BUCK_VBUCK5_RC8_OP_EN_ADDR 0x170E
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#define MT6363_RG_BUCK_VBUCK5_RC9_OP_EN_ADDR 0x170E
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#define MT6363_RG_BUCK_VBUCK5_RC10_OP_EN_ADDR 0x170E
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#define MT6363_RG_BUCK_VBUCK5_RC11_OP_EN_ADDR 0x170E
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#define MT6363_RG_BUCK_VBUCK5_RC12_OP_EN_ADDR 0x170E
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#define MT6363_RG_BUCK_VBUCK5_RC13_OP_EN_ADDR 0x170E
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#define MT6363_RG_BUCK_VBUCK5_HW0_OP_EN_ADDR 0x170F
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#define MT6363_RG_BUCK_VBUCK5_HW1_OP_EN_ADDR 0x170F
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#define MT6363_RG_BUCK_VBUCK5_HW2_OP_EN_ADDR 0x170F
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#define MT6363_RG_BUCK_VBUCK5_HW3_OP_EN_ADDR 0x170F
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#define MT6363_RG_BUCK_VBUCK5_SW_OP_EN_ADDR 0x170F
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#define MT6363_RG_BUCK_VBUCK5_RC0_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC1_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC2_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC3_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC4_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC5_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC6_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC7_OP_CFG_ADDR 0x1710
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#define MT6363_RG_BUCK_VBUCK5_RC8_OP_CFG_ADDR 0x1711
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#define MT6363_RG_BUCK_VBUCK5_RC9_OP_CFG_ADDR 0x1711
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#define MT6363_RG_BUCK_VBUCK5_RC10_OP_CFG_ADDR 0x1711
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#define MT6363_RG_BUCK_VBUCK5_RC11_OP_CFG_ADDR 0x1711
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#define MT6363_RG_BUCK_VBUCK5_RC12_OP_CFG_ADDR 0x1711
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#define MT6363_RG_BUCK_VBUCK5_RC13_OP_CFG_ADDR 0x1711
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#define MT6363_RG_BUCK_VBUCK5_HW0_OP_CFG_ADDR 0x1712
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#define MT6363_RG_BUCK_VBUCK5_HW1_OP_CFG_ADDR 0x1712
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#define MT6363_RG_BUCK_VBUCK5_HW2_OP_CFG_ADDR 0x1712
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#define MT6363_RG_BUCK_VBUCK5_HW3_OP_CFG_ADDR 0x1712
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#define MT6363_RG_BUCK_VBUCK5_RC0_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC1_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC2_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC3_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC4_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC5_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC6_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC7_OP_MODE_ADDR 0x1713
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#define MT6363_RG_BUCK_VBUCK5_RC8_OP_MODE_ADDR 0x1714
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#define MT6363_RG_BUCK_VBUCK5_RC9_OP_MODE_ADDR 0x1714
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#define MT6363_RG_BUCK_VBUCK5_RC10_OP_MODE_ADDR 0x1714
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#define MT6363_RG_BUCK_VBUCK5_RC11_OP_MODE_ADDR 0x1714
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#define MT6363_RG_BUCK_VBUCK5_RC12_OP_MODE_ADDR 0x1714
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#define MT6363_RG_BUCK_VBUCK5_RC13_OP_MODE_ADDR 0x1714
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#define MT6363_RG_BUCK_VBUCK5_HW0_OP_MODE_ADDR 0x1715
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#define MT6363_RG_BUCK_VBUCK5_HW1_OP_MODE_ADDR 0x1715
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#define MT6363_RG_BUCK_VBUCK5_HW2_OP_MODE_ADDR 0x1715
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#define MT6363_RG_BUCK_VBUCK5_HW3_OP_MODE_ADDR 0x1715
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#define MT6363_RG_BUCK_VBUCK6_VOSEL_SLEEP_ADDR 0x1787
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#define MT6363_RG_BUCK_VBUCK6_ONLV_EN_ADDR 0x1788
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#define MT6363_RG_BUCK_VBUCK6_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VBUCK6_RC0_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC1_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC2_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC3_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC4_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC5_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC6_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC7_OP_EN_ADDR 0x178D
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#define MT6363_RG_BUCK_VBUCK6_RC8_OP_EN_ADDR 0x178E
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#define MT6363_RG_BUCK_VBUCK6_RC9_OP_EN_ADDR 0x178E
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#define MT6363_RG_BUCK_VBUCK6_RC10_OP_EN_ADDR 0x178E
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#define MT6363_RG_BUCK_VBUCK6_RC11_OP_EN_ADDR 0x178E
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#define MT6363_RG_BUCK_VBUCK6_RC12_OP_EN_ADDR 0x178E
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#define MT6363_RG_BUCK_VBUCK6_RC13_OP_EN_ADDR 0x178E
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#define MT6363_RG_BUCK_VBUCK6_HW0_OP_EN_ADDR 0x178F
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#define MT6363_RG_BUCK_VBUCK6_HW1_OP_EN_ADDR 0x178F
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#define MT6363_RG_BUCK_VBUCK6_HW2_OP_EN_ADDR 0x178F
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#define MT6363_RG_BUCK_VBUCK6_HW3_OP_EN_ADDR 0x178F
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#define MT6363_RG_BUCK_VBUCK6_SW_OP_EN_ADDR 0x178F
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#define MT6363_RG_BUCK_VBUCK6_RC0_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC1_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC2_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC3_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC4_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC5_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC6_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC7_OP_CFG_ADDR 0x1790
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#define MT6363_RG_BUCK_VBUCK6_RC8_OP_CFG_ADDR 0x1791
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#define MT6363_RG_BUCK_VBUCK6_RC9_OP_CFG_ADDR 0x1791
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#define MT6363_RG_BUCK_VBUCK6_RC10_OP_CFG_ADDR 0x1791
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#define MT6363_RG_BUCK_VBUCK6_RC11_OP_CFG_ADDR 0x1791
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#define MT6363_RG_BUCK_VBUCK6_RC12_OP_CFG_ADDR 0x1791
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#define MT6363_RG_BUCK_VBUCK6_RC13_OP_CFG_ADDR 0x1791
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#define MT6363_RG_BUCK_VBUCK6_HW0_OP_CFG_ADDR 0x1792
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#define MT6363_RG_BUCK_VBUCK6_HW1_OP_CFG_ADDR 0x1792
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#define MT6363_RG_BUCK_VBUCK6_HW2_OP_CFG_ADDR 0x1792
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#define MT6363_RG_BUCK_VBUCK6_HW3_OP_CFG_ADDR 0x1792
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#define MT6363_RG_BUCK_VBUCK6_RC0_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC1_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC2_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC3_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC4_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC5_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC6_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC7_OP_MODE_ADDR 0x1793
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#define MT6363_RG_BUCK_VBUCK6_RC8_OP_MODE_ADDR 0x1794
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#define MT6363_RG_BUCK_VBUCK6_RC9_OP_MODE_ADDR 0x1794
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#define MT6363_RG_BUCK_VBUCK6_RC10_OP_MODE_ADDR 0x1794
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#define MT6363_RG_BUCK_VBUCK6_RC11_OP_MODE_ADDR 0x1794
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#define MT6363_RG_BUCK_VBUCK6_RC12_OP_MODE_ADDR 0x1794
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#define MT6363_RG_BUCK_VBUCK6_RC13_OP_MODE_ADDR 0x1794
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#define MT6363_RG_BUCK_VBUCK6_HW0_OP_MODE_ADDR 0x1795
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#define MT6363_RG_BUCK_VBUCK6_HW1_OP_MODE_ADDR 0x1795
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#define MT6363_RG_BUCK_VBUCK6_HW2_OP_MODE_ADDR 0x1795
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#define MT6363_RG_BUCK_VBUCK6_HW3_OP_MODE_ADDR 0x1795
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#define MT6363_RG_BUCK_VBUCK7_VOSEL_SLEEP_ADDR 0x1807
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#define MT6363_RG_BUCK_VBUCK7_ONLV_EN_ADDR 0x1808
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#define MT6363_RG_BUCK_VBUCK7_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VBUCK7_RC0_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC1_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC2_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC3_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC4_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC5_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC6_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC7_OP_EN_ADDR 0x180D
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#define MT6363_RG_BUCK_VBUCK7_RC8_OP_EN_ADDR 0x180E
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#define MT6363_RG_BUCK_VBUCK7_RC9_OP_EN_ADDR 0x180E
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#define MT6363_RG_BUCK_VBUCK7_RC10_OP_EN_ADDR 0x180E
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#define MT6363_RG_BUCK_VBUCK7_RC11_OP_EN_ADDR 0x180E
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#define MT6363_RG_BUCK_VBUCK7_RC12_OP_EN_ADDR 0x180E
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#define MT6363_RG_BUCK_VBUCK7_RC13_OP_EN_ADDR 0x180E
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#define MT6363_RG_BUCK_VBUCK7_HW0_OP_EN_ADDR 0x180F
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#define MT6363_RG_BUCK_VBUCK7_HW1_OP_EN_ADDR 0x180F
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#define MT6363_RG_BUCK_VBUCK7_HW2_OP_EN_ADDR 0x180F
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#define MT6363_RG_BUCK_VBUCK7_HW3_OP_EN_ADDR 0x180F
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#define MT6363_RG_BUCK_VBUCK7_SW_OP_EN_ADDR 0x180F
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#define MT6363_RG_BUCK_VBUCK7_RC0_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC1_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC2_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC3_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC4_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC5_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC6_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC7_OP_CFG_ADDR 0x1810
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#define MT6363_RG_BUCK_VBUCK7_RC8_OP_CFG_ADDR 0x1811
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#define MT6363_RG_BUCK_VBUCK7_RC9_OP_CFG_ADDR 0x1811
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#define MT6363_RG_BUCK_VBUCK7_RC10_OP_CFG_ADDR 0x1811
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#define MT6363_RG_BUCK_VBUCK7_RC11_OP_CFG_ADDR 0x1811
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#define MT6363_RG_BUCK_VBUCK7_RC12_OP_CFG_ADDR 0x1811
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#define MT6363_RG_BUCK_VBUCK7_RC13_OP_CFG_ADDR 0x1811
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#define MT6363_RG_BUCK_VBUCK7_HW0_OP_CFG_ADDR 0x1812
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#define MT6363_RG_BUCK_VBUCK7_HW1_OP_CFG_ADDR 0x1812
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#define MT6363_RG_BUCK_VBUCK7_HW2_OP_CFG_ADDR 0x1812
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#define MT6363_RG_BUCK_VBUCK7_HW3_OP_CFG_ADDR 0x1812
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#define MT6363_RG_BUCK_VBUCK7_RC0_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC1_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC2_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC3_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC4_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC5_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC6_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC7_OP_MODE_ADDR 0x1813
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#define MT6363_RG_BUCK_VBUCK7_RC8_OP_MODE_ADDR 0x1814
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#define MT6363_RG_BUCK_VBUCK7_RC9_OP_MODE_ADDR 0x1814
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#define MT6363_RG_BUCK_VBUCK7_RC10_OP_MODE_ADDR 0x1814
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#define MT6363_RG_BUCK_VBUCK7_RC11_OP_MODE_ADDR 0x1814
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#define MT6363_RG_BUCK_VBUCK7_RC12_OP_MODE_ADDR 0x1814
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#define MT6363_RG_BUCK_VBUCK7_RC13_OP_MODE_ADDR 0x1814
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#define MT6363_RG_BUCK_VBUCK7_HW0_OP_MODE_ADDR 0x1815
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#define MT6363_RG_BUCK_VBUCK7_HW1_OP_MODE_ADDR 0x1815
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#define MT6363_RG_BUCK_VBUCK7_HW2_OP_MODE_ADDR 0x1815
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#define MT6363_RG_BUCK_VBUCK7_HW3_OP_MODE_ADDR 0x1815
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#define MT6363_RG_BUCK_VS1_VOSEL_SLEEP_ADDR 0x1887
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#define MT6363_RG_BUCK_VS1_ONLV_EN_ADDR 0x1888
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#define MT6363_RG_BUCK_VS1_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VS1_RC0_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC1_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC2_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC3_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC4_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC5_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC6_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC7_OP_EN_ADDR 0x188D
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#define MT6363_RG_BUCK_VS1_RC8_OP_EN_ADDR 0x188E
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#define MT6363_RG_BUCK_VS1_RC9_OP_EN_ADDR 0x188E
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#define MT6363_RG_BUCK_VS1_RC10_OP_EN_ADDR 0x188E
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#define MT6363_RG_BUCK_VS1_RC11_OP_EN_ADDR 0x188E
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#define MT6363_RG_BUCK_VS1_RC12_OP_EN_ADDR 0x188E
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#define MT6363_RG_BUCK_VS1_RC13_OP_EN_ADDR 0x188E
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#define MT6363_RG_BUCK_VS1_HW0_OP_EN_ADDR 0x188F
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#define MT6363_RG_BUCK_VS1_HW1_OP_EN_ADDR 0x188F
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#define MT6363_RG_BUCK_VS1_HW2_OP_EN_ADDR 0x188F
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#define MT6363_RG_BUCK_VS1_HW3_OP_EN_ADDR 0x188F
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#define MT6363_RG_BUCK_VS1_HW4_OP_EN_ADDR 0x188F
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#define MT6363_RG_BUCK_VS1_SW_OP_EN_ADDR 0x188F
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#define MT6363_RG_BUCK_VS1_RC0_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC1_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC2_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC3_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC4_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC5_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC6_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC7_OP_CFG_ADDR 0x1890
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#define MT6363_RG_BUCK_VS1_RC8_OP_CFG_ADDR 0x1891
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#define MT6363_RG_BUCK_VS1_RC9_OP_CFG_ADDR 0x1891
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#define MT6363_RG_BUCK_VS1_RC10_OP_CFG_ADDR 0x1891
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#define MT6363_RG_BUCK_VS1_RC11_OP_CFG_ADDR 0x1891
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#define MT6363_RG_BUCK_VS1_RC12_OP_CFG_ADDR 0x1891
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#define MT6363_RG_BUCK_VS1_RC13_OP_CFG_ADDR 0x1891
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#define MT6363_RG_BUCK_VS1_HW0_OP_CFG_ADDR 0x1892
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#define MT6363_RG_BUCK_VS1_HW1_OP_CFG_ADDR 0x1892
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#define MT6363_RG_BUCK_VS1_HW2_OP_CFG_ADDR 0x1892
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#define MT6363_RG_BUCK_VS1_HW3_OP_CFG_ADDR 0x1892
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#define MT6363_RG_BUCK_VS1_HW4_OP_CFG_ADDR 0x1892
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#define MT6363_RG_BUCK_VS1_RC0_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC1_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC2_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC3_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC4_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC5_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC6_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC7_OP_MODE_ADDR 0x1893
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#define MT6363_RG_BUCK_VS1_RC8_OP_MODE_ADDR 0x1894
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#define MT6363_RG_BUCK_VS1_RC9_OP_MODE_ADDR 0x1894
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#define MT6363_RG_BUCK_VS1_RC10_OP_MODE_ADDR 0x1894
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#define MT6363_RG_BUCK_VS1_RC11_OP_MODE_ADDR 0x1894
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#define MT6363_RG_BUCK_VS1_RC12_OP_MODE_ADDR 0x1894
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#define MT6363_RG_BUCK_VS1_RC13_OP_MODE_ADDR 0x1894
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#define MT6363_RG_BUCK_VS1_HW0_OP_MODE_ADDR 0x1895
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#define MT6363_RG_BUCK_VS1_HW1_OP_MODE_ADDR 0x1895
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#define MT6363_RG_BUCK_VS1_HW2_OP_MODE_ADDR 0x1895
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#define MT6363_RG_BUCK_VS1_HW3_OP_MODE_ADDR 0x1895
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#define MT6363_RG_BUCK_VS1_HW4_OP_MODE_ADDR 0x1895
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#define MT6363_RG_BUCK_VS3_VOSEL_SLEEP_ADDR 0x1907
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#define MT6363_RG_BUCK_VS3_ONLV_EN_ADDR 0x1908
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#define MT6363_RG_BUCK_VS3_ONLV_EN_SHIFT 4
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#define MT6363_RG_BUCK_VS3_RC0_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC1_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC2_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC3_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC4_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC5_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC6_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC7_OP_EN_ADDR 0x190D
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#define MT6363_RG_BUCK_VS3_RC8_OP_EN_ADDR 0x190E
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#define MT6363_RG_BUCK_VS3_RC9_OP_EN_ADDR 0x190E
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#define MT6363_RG_BUCK_VS3_RC10_OP_EN_ADDR 0x190E
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#define MT6363_RG_BUCK_VS3_RC11_OP_EN_ADDR 0x190E
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#define MT6363_RG_BUCK_VS3_RC12_OP_EN_ADDR 0x190E
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#define MT6363_RG_BUCK_VS3_RC13_OP_EN_ADDR 0x190E
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#define MT6363_RG_BUCK_VS3_HW0_OP_EN_ADDR 0x190F
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#define MT6363_RG_BUCK_VS3_HW1_OP_EN_ADDR 0x190F
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#define MT6363_RG_BUCK_VS3_HW2_OP_EN_ADDR 0x190F
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#define MT6363_RG_BUCK_VS3_HW3_OP_EN_ADDR 0x190F
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#define MT6363_RG_BUCK_VS3_HW4_OP_EN_ADDR 0x190F
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#define MT6363_RG_BUCK_VS3_SW_OP_EN_ADDR 0x190F
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#define MT6363_RG_BUCK_VS3_RC0_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC1_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC2_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC3_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC4_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC5_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC6_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC7_OP_CFG_ADDR 0x1910
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#define MT6363_RG_BUCK_VS3_RC8_OP_CFG_ADDR 0x1911
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#define MT6363_RG_BUCK_VS3_RC9_OP_CFG_ADDR 0x1911
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#define MT6363_RG_BUCK_VS3_RC10_OP_CFG_ADDR 0x1911
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#define MT6363_RG_BUCK_VS3_RC11_OP_CFG_ADDR 0x1911
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#define MT6363_RG_BUCK_VS3_RC12_OP_CFG_ADDR 0x1911
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#define MT6363_RG_BUCK_VS3_RC13_OP_CFG_ADDR 0x1911
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#define MT6363_RG_BUCK_VS3_HW0_OP_CFG_ADDR 0x1912
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#define MT6363_RG_BUCK_VS3_HW1_OP_CFG_ADDR 0x1912
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#define MT6363_RG_BUCK_VS3_HW2_OP_CFG_ADDR 0x1912
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#define MT6363_RG_BUCK_VS3_HW3_OP_CFG_ADDR 0x1912
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#define MT6363_RG_BUCK_VS3_HW4_OP_CFG_ADDR 0x1912
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#define MT6363_RG_BUCK_VS3_RC0_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC1_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC2_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC3_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC4_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC5_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC6_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC7_OP_MODE_ADDR 0x1913
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#define MT6363_RG_BUCK_VS3_RC8_OP_MODE_ADDR 0x1914
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#define MT6363_RG_BUCK_VS3_RC9_OP_MODE_ADDR 0x1914
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#define MT6363_RG_BUCK_VS3_RC10_OP_MODE_ADDR 0x1914
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#define MT6363_RG_BUCK_VS3_RC11_OP_MODE_ADDR 0x1914
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#define MT6363_RG_BUCK_VS3_RC12_OP_MODE_ADDR 0x1914
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#define MT6363_RG_BUCK_VS3_RC13_OP_MODE_ADDR 0x1914
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#define MT6363_RG_BUCK_VS3_HW0_OP_MODE_ADDR 0x1915
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#define MT6363_RG_BUCK_VS3_HW1_OP_MODE_ADDR 0x1915
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#define MT6363_RG_BUCK_VS3_HW2_OP_MODE_ADDR 0x1915
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#define MT6363_RG_BUCK_VS3_HW3_OP_MODE_ADDR 0x1915
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#define MT6363_RG_BUCK_VS3_HW4_OP_MODE_ADDR 0x1915
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#define MT6363_RG_LDO_VCN15_ONLV_EN_ADDR 0x1B88
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#define MT6363_RG_LDO_VCN15_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VCN15_RC0_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC1_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC2_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC3_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC4_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC5_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC6_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC7_OP_EN_ADDR 0x1B8C
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#define MT6363_RG_LDO_VCN15_RC8_OP_EN_ADDR 0x1B8D
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#define MT6363_RG_LDO_VCN15_RC9_OP_EN_ADDR 0x1B8D
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#define MT6363_RG_LDO_VCN15_RC10_OP_EN_ADDR 0x1B8D
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#define MT6363_RG_LDO_VCN15_RC11_OP_EN_ADDR 0x1B8D
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#define MT6363_RG_LDO_VCN15_RC12_OP_EN_ADDR 0x1B8D
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#define MT6363_RG_LDO_VCN15_RC13_OP_EN_ADDR 0x1B8D
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#define MT6363_RG_LDO_VCN15_HW0_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_HW1_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_HW2_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_HW3_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_HW4_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_HW5_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_HW6_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_SW_OP_EN_ADDR 0x1B8E
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#define MT6363_RG_LDO_VCN15_RC0_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC1_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC2_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC3_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC4_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC5_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC6_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC7_OP_CFG_ADDR 0x1B8F
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#define MT6363_RG_LDO_VCN15_RC8_OP_CFG_ADDR 0x1B90
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#define MT6363_RG_LDO_VCN15_RC9_OP_CFG_ADDR 0x1B90
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#define MT6363_RG_LDO_VCN15_RC10_OP_CFG_ADDR 0x1B90
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#define MT6363_RG_LDO_VCN15_RC11_OP_CFG_ADDR 0x1B90
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#define MT6363_RG_LDO_VCN15_RC12_OP_CFG_ADDR 0x1B90
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#define MT6363_RG_LDO_VCN15_RC13_OP_CFG_ADDR 0x1B90
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#define MT6363_RG_LDO_VCN15_HW0_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_HW1_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_HW2_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_HW3_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_HW4_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_HW5_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_HW6_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_SW_OP_CFG_ADDR 0x1B91
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#define MT6363_RG_LDO_VCN15_RC0_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC1_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC2_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC3_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC4_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC5_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC6_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC7_OP_MODE_ADDR 0x1B92
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#define MT6363_RG_LDO_VCN15_RC8_OP_MODE_ADDR 0x1B93
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#define MT6363_RG_LDO_VCN15_RC9_OP_MODE_ADDR 0x1B93
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#define MT6363_RG_LDO_VCN15_RC10_OP_MODE_ADDR 0x1B93
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#define MT6363_RG_LDO_VCN15_RC11_OP_MODE_ADDR 0x1B93
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#define MT6363_RG_LDO_VCN15_RC12_OP_MODE_ADDR 0x1B93
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#define MT6363_RG_LDO_VCN15_RC13_OP_MODE_ADDR 0x1B93
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#define MT6363_RG_LDO_VCN15_HW0_OP_MODE_ADDR 0x1B94
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#define MT6363_RG_LDO_VCN15_HW1_OP_MODE_ADDR 0x1B94
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#define MT6363_RG_LDO_VCN15_HW2_OP_MODE_ADDR 0x1B94
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|
#define MT6363_RG_LDO_VCN15_HW3_OP_MODE_ADDR 0x1B94
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#define MT6363_RG_LDO_VCN15_HW4_OP_MODE_ADDR 0x1B94
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|
#define MT6363_RG_LDO_VCN15_HW5_OP_MODE_ADDR 0x1B94
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|
#define MT6363_RG_LDO_VCN15_HW6_OP_MODE_ADDR 0x1B94
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|
#define MT6363_RG_LDO_VRF09_ONLV_EN_ADDR 0x1B96
|
|
#define MT6363_RG_LDO_VRF09_ONLV_EN_SHIFT 3
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|
#define MT6363_RG_LDO_VRF09_RC0_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC1_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC2_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC3_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC4_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC5_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC6_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC7_OP_EN_ADDR 0x1B9A
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#define MT6363_RG_LDO_VRF09_RC8_OP_EN_ADDR 0x1B9B
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#define MT6363_RG_LDO_VRF09_RC9_OP_EN_ADDR 0x1B9B
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#define MT6363_RG_LDO_VRF09_RC10_OP_EN_ADDR 0x1B9B
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|
#define MT6363_RG_LDO_VRF09_RC11_OP_EN_ADDR 0x1B9B
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|
#define MT6363_RG_LDO_VRF09_RC12_OP_EN_ADDR 0x1B9B
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#define MT6363_RG_LDO_VRF09_RC13_OP_EN_ADDR 0x1B9B
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|
#define MT6363_RG_LDO_VRF09_HW0_OP_EN_ADDR 0x1B9C
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|
#define MT6363_RG_LDO_VRF09_HW1_OP_EN_ADDR 0x1B9C
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|
#define MT6363_RG_LDO_VRF09_HW2_OP_EN_ADDR 0x1B9C
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|
#define MT6363_RG_LDO_VRF09_HW3_OP_EN_ADDR 0x1B9C
|
|
#define MT6363_RG_LDO_VRF09_HW4_OP_EN_ADDR 0x1B9C
|
|
#define MT6363_RG_LDO_VRF09_HW5_OP_EN_ADDR 0x1B9C
|
|
#define MT6363_RG_LDO_VRF09_HW6_OP_EN_ADDR 0x1B9C
|
|
#define MT6363_RG_LDO_VRF09_SW_OP_EN_ADDR 0x1B9C
|
|
#define MT6363_RG_LDO_VRF09_RC0_OP_CFG_ADDR 0x1B9D
|
|
#define MT6363_RG_LDO_VRF09_RC1_OP_CFG_ADDR 0x1B9D
|
|
#define MT6363_RG_LDO_VRF09_RC2_OP_CFG_ADDR 0x1B9D
|
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#define MT6363_RG_LDO_VRF09_RC3_OP_CFG_ADDR 0x1B9D
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#define MT6363_RG_LDO_VRF09_RC4_OP_CFG_ADDR 0x1B9D
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#define MT6363_RG_LDO_VRF09_RC5_OP_CFG_ADDR 0x1B9D
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#define MT6363_RG_LDO_VRF09_RC6_OP_CFG_ADDR 0x1B9D
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#define MT6363_RG_LDO_VRF09_RC7_OP_CFG_ADDR 0x1B9D
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#define MT6363_RG_LDO_VRF09_RC8_OP_CFG_ADDR 0x1B9E
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#define MT6363_RG_LDO_VRF09_RC9_OP_CFG_ADDR 0x1B9E
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#define MT6363_RG_LDO_VRF09_RC10_OP_CFG_ADDR 0x1B9E
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#define MT6363_RG_LDO_VRF09_RC11_OP_CFG_ADDR 0x1B9E
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#define MT6363_RG_LDO_VRF09_RC12_OP_CFG_ADDR 0x1B9E
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#define MT6363_RG_LDO_VRF09_RC13_OP_CFG_ADDR 0x1B9E
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#define MT6363_RG_LDO_VRF09_HW0_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_HW1_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_HW2_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_HW3_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_HW4_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_HW5_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_HW6_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_SW_OP_CFG_ADDR 0x1B9F
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#define MT6363_RG_LDO_VRF09_RC0_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC1_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC2_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC3_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC4_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC5_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC6_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC7_OP_MODE_ADDR 0x1BA0
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#define MT6363_RG_LDO_VRF09_RC8_OP_MODE_ADDR 0x1BA1
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#define MT6363_RG_LDO_VRF09_RC9_OP_MODE_ADDR 0x1BA1
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#define MT6363_RG_LDO_VRF09_RC10_OP_MODE_ADDR 0x1BA1
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#define MT6363_RG_LDO_VRF09_RC11_OP_MODE_ADDR 0x1BA1
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#define MT6363_RG_LDO_VRF09_RC12_OP_MODE_ADDR 0x1BA1
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#define MT6363_RG_LDO_VRF09_RC13_OP_MODE_ADDR 0x1BA1
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#define MT6363_RG_LDO_VRF09_HW0_OP_MODE_ADDR 0x1BA2
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#define MT6363_RG_LDO_VRF09_HW1_OP_MODE_ADDR 0x1BA2
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#define MT6363_RG_LDO_VRF09_HW2_OP_MODE_ADDR 0x1BA2
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#define MT6363_RG_LDO_VRF09_HW3_OP_MODE_ADDR 0x1BA2
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#define MT6363_RG_LDO_VRF09_HW4_OP_MODE_ADDR 0x1BA2
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#define MT6363_RG_LDO_VRF09_HW5_OP_MODE_ADDR 0x1BA2
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#define MT6363_RG_LDO_VRF09_HW6_OP_MODE_ADDR 0x1BA2
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#define MT6363_RG_LDO_VRF12_ONLV_EN_ADDR 0x1BA4
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#define MT6363_RG_LDO_VRF12_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VRF12_RC0_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC1_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC2_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC3_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC4_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC5_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC6_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC7_OP_EN_ADDR 0x1BA8
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#define MT6363_RG_LDO_VRF12_RC8_OP_EN_ADDR 0x1BA9
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#define MT6363_RG_LDO_VRF12_RC9_OP_EN_ADDR 0x1BA9
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#define MT6363_RG_LDO_VRF12_RC10_OP_EN_ADDR 0x1BA9
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#define MT6363_RG_LDO_VRF12_RC11_OP_EN_ADDR 0x1BA9
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#define MT6363_RG_LDO_VRF12_RC12_OP_EN_ADDR 0x1BA9
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#define MT6363_RG_LDO_VRF12_RC13_OP_EN_ADDR 0x1BA9
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#define MT6363_RG_LDO_VRF12_HW0_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_HW1_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_HW2_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_HW3_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_HW4_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_HW5_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_HW6_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_SW_OP_EN_ADDR 0x1BAA
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#define MT6363_RG_LDO_VRF12_RC0_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC1_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC2_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC3_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC4_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC5_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC6_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC7_OP_CFG_ADDR 0x1BAB
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#define MT6363_RG_LDO_VRF12_RC8_OP_CFG_ADDR 0x1BAC
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#define MT6363_RG_LDO_VRF12_RC9_OP_CFG_ADDR 0x1BAC
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#define MT6363_RG_LDO_VRF12_RC10_OP_CFG_ADDR 0x1BAC
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#define MT6363_RG_LDO_VRF12_RC11_OP_CFG_ADDR 0x1BAC
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#define MT6363_RG_LDO_VRF12_RC12_OP_CFG_ADDR 0x1BAC
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#define MT6363_RG_LDO_VRF12_RC13_OP_CFG_ADDR 0x1BAC
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#define MT6363_RG_LDO_VRF12_HW0_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_HW1_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_HW2_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_HW3_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_HW4_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_HW5_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_HW6_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_SW_OP_CFG_ADDR 0x1BAD
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#define MT6363_RG_LDO_VRF12_RC0_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC1_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC2_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC3_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC4_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC5_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC6_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC7_OP_MODE_ADDR 0x1BAE
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#define MT6363_RG_LDO_VRF12_RC8_OP_MODE_ADDR 0x1BAF
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#define MT6363_RG_LDO_VRF12_RC9_OP_MODE_ADDR 0x1BAF
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#define MT6363_RG_LDO_VRF12_RC10_OP_MODE_ADDR 0x1BAF
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#define MT6363_RG_LDO_VRF12_RC11_OP_MODE_ADDR 0x1BAF
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#define MT6363_RG_LDO_VRF12_RC12_OP_MODE_ADDR 0x1BAF
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#define MT6363_RG_LDO_VRF12_RC13_OP_MODE_ADDR 0x1BAF
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#define MT6363_RG_LDO_VRF12_HW0_OP_MODE_ADDR 0x1BB0
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#define MT6363_RG_LDO_VRF12_HW1_OP_MODE_ADDR 0x1BB0
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#define MT6363_RG_LDO_VRF12_HW2_OP_MODE_ADDR 0x1BB0
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#define MT6363_RG_LDO_VRF12_HW3_OP_MODE_ADDR 0x1BB0
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#define MT6363_RG_LDO_VRF12_HW4_OP_MODE_ADDR 0x1BB0
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#define MT6363_RG_LDO_VRF12_HW5_OP_MODE_ADDR 0x1BB0
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#define MT6363_RG_LDO_VRF12_HW6_OP_MODE_ADDR 0x1BB0
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#define MT6363_RG_LDO_VRF13_ONLV_EN_ADDR 0x1BB2
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#define MT6363_RG_LDO_VRF13_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VRF13_RC0_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC1_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC2_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC3_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC4_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC5_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC6_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC7_OP_EN_ADDR 0x1BB6
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#define MT6363_RG_LDO_VRF13_RC8_OP_EN_ADDR 0x1BB7
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#define MT6363_RG_LDO_VRF13_RC9_OP_EN_ADDR 0x1BB7
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#define MT6363_RG_LDO_VRF13_RC10_OP_EN_ADDR 0x1BB7
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#define MT6363_RG_LDO_VRF13_RC11_OP_EN_ADDR 0x1BB7
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#define MT6363_RG_LDO_VRF13_RC12_OP_EN_ADDR 0x1BB7
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#define MT6363_RG_LDO_VRF13_RC13_OP_EN_ADDR 0x1BB7
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#define MT6363_RG_LDO_VRF13_HW0_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_HW1_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_HW2_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_HW3_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_HW4_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_HW5_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_HW6_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_SW_OP_EN_ADDR 0x1BB8
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#define MT6363_RG_LDO_VRF13_RC0_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC1_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC2_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC3_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC4_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC5_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC6_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC7_OP_CFG_ADDR 0x1BB9
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#define MT6363_RG_LDO_VRF13_RC8_OP_CFG_ADDR 0x1BBA
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#define MT6363_RG_LDO_VRF13_RC9_OP_CFG_ADDR 0x1BBA
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#define MT6363_RG_LDO_VRF13_RC10_OP_CFG_ADDR 0x1BBA
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#define MT6363_RG_LDO_VRF13_RC11_OP_CFG_ADDR 0x1BBA
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#define MT6363_RG_LDO_VRF13_RC12_OP_CFG_ADDR 0x1BBA
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#define MT6363_RG_LDO_VRF13_RC13_OP_CFG_ADDR 0x1BBA
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#define MT6363_RG_LDO_VRF13_HW0_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_HW1_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_HW2_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_HW3_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_HW4_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_HW5_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_HW6_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_SW_OP_CFG_ADDR 0x1BBB
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#define MT6363_RG_LDO_VRF13_RC0_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC1_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC2_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC3_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC4_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC5_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC6_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC7_OP_MODE_ADDR 0x1BBC
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#define MT6363_RG_LDO_VRF13_RC8_OP_MODE_ADDR 0x1BBD
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#define MT6363_RG_LDO_VRF13_RC9_OP_MODE_ADDR 0x1BBD
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#define MT6363_RG_LDO_VRF13_RC10_OP_MODE_ADDR 0x1BBD
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#define MT6363_RG_LDO_VRF13_RC11_OP_MODE_ADDR 0x1BBD
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#define MT6363_RG_LDO_VRF13_RC12_OP_MODE_ADDR 0x1BBD
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#define MT6363_RG_LDO_VRF13_RC13_OP_MODE_ADDR 0x1BBD
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#define MT6363_RG_LDO_VRF13_HW0_OP_MODE_ADDR 0x1BBE
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#define MT6363_RG_LDO_VRF13_HW1_OP_MODE_ADDR 0x1BBE
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#define MT6363_RG_LDO_VRF13_HW2_OP_MODE_ADDR 0x1BBE
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#define MT6363_RG_LDO_VRF13_HW3_OP_MODE_ADDR 0x1BBE
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#define MT6363_RG_LDO_VRF13_HW4_OP_MODE_ADDR 0x1BBE
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#define MT6363_RG_LDO_VRF13_HW5_OP_MODE_ADDR 0x1BBE
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#define MT6363_RG_LDO_VRF13_HW6_OP_MODE_ADDR 0x1BBE
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#define MT6363_RG_LDO_VRF18_ONLV_EN_ADDR 0x1BC0
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#define MT6363_RG_LDO_VRF18_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VRF18_RC0_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC1_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC2_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC3_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC4_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC5_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC6_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC7_OP_EN_ADDR 0x1BC4
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#define MT6363_RG_LDO_VRF18_RC8_OP_EN_ADDR 0x1BC5
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#define MT6363_RG_LDO_VRF18_RC9_OP_EN_ADDR 0x1BC5
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#define MT6363_RG_LDO_VRF18_RC10_OP_EN_ADDR 0x1BC5
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#define MT6363_RG_LDO_VRF18_RC11_OP_EN_ADDR 0x1BC5
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#define MT6363_RG_LDO_VRF18_RC12_OP_EN_ADDR 0x1BC5
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#define MT6363_RG_LDO_VRF18_RC13_OP_EN_ADDR 0x1BC5
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#define MT6363_RG_LDO_VRF18_HW0_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_HW1_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_HW2_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_HW3_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_HW4_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_HW5_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_HW6_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_SW_OP_EN_ADDR 0x1BC6
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#define MT6363_RG_LDO_VRF18_RC0_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC1_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC2_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC3_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC4_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC5_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC6_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC7_OP_CFG_ADDR 0x1BC7
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#define MT6363_RG_LDO_VRF18_RC8_OP_CFG_ADDR 0x1BC8
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#define MT6363_RG_LDO_VRF18_RC9_OP_CFG_ADDR 0x1BC8
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#define MT6363_RG_LDO_VRF18_RC10_OP_CFG_ADDR 0x1BC8
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#define MT6363_RG_LDO_VRF18_RC11_OP_CFG_ADDR 0x1BC8
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#define MT6363_RG_LDO_VRF18_RC12_OP_CFG_ADDR 0x1BC8
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#define MT6363_RG_LDO_VRF18_RC13_OP_CFG_ADDR 0x1BC8
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#define MT6363_RG_LDO_VRF18_HW0_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_HW1_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_HW2_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_HW3_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_HW4_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_HW5_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_HW6_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_SW_OP_CFG_ADDR 0x1BC9
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#define MT6363_RG_LDO_VRF18_RC0_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC1_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC2_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC3_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC4_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC5_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC6_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC7_OP_MODE_ADDR 0x1BCA
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#define MT6363_RG_LDO_VRF18_RC8_OP_MODE_ADDR 0x1BCB
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#define MT6363_RG_LDO_VRF18_RC9_OP_MODE_ADDR 0x1BCB
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#define MT6363_RG_LDO_VRF18_RC10_OP_MODE_ADDR 0x1BCB
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#define MT6363_RG_LDO_VRF18_RC11_OP_MODE_ADDR 0x1BCB
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#define MT6363_RG_LDO_VRF18_RC12_OP_MODE_ADDR 0x1BCB
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#define MT6363_RG_LDO_VRF18_RC13_OP_MODE_ADDR 0x1BCB
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#define MT6363_RG_LDO_VRF18_HW0_OP_MODE_ADDR 0x1BCC
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#define MT6363_RG_LDO_VRF18_HW1_OP_MODE_ADDR 0x1BCC
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#define MT6363_RG_LDO_VRF18_HW2_OP_MODE_ADDR 0x1BCC
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#define MT6363_RG_LDO_VRF18_HW3_OP_MODE_ADDR 0x1BCC
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#define MT6363_RG_LDO_VRF18_HW4_OP_MODE_ADDR 0x1BCC
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#define MT6363_RG_LDO_VRF18_HW5_OP_MODE_ADDR 0x1BCC
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#define MT6363_RG_LDO_VRF18_HW6_OP_MODE_ADDR 0x1BCC
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#define MT6363_RG_LDO_VRFIO18_ONLV_EN_ADDR 0x1BCE
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#define MT6363_RG_LDO_VRFIO18_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VRFIO18_RC0_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC1_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC2_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC3_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC4_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC5_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC6_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC7_OP_EN_ADDR 0x1BD2
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#define MT6363_RG_LDO_VRFIO18_RC8_OP_EN_ADDR 0x1BD3
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#define MT6363_RG_LDO_VRFIO18_RC9_OP_EN_ADDR 0x1BD3
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#define MT6363_RG_LDO_VRFIO18_RC10_OP_EN_ADDR 0x1BD3
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#define MT6363_RG_LDO_VRFIO18_RC11_OP_EN_ADDR 0x1BD3
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#define MT6363_RG_LDO_VRFIO18_RC12_OP_EN_ADDR 0x1BD3
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#define MT6363_RG_LDO_VRFIO18_RC13_OP_EN_ADDR 0x1BD3
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#define MT6363_RG_LDO_VRFIO18_HW0_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_HW1_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_HW2_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_HW3_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_HW4_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_HW5_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_HW6_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_SW_OP_EN_ADDR 0x1BD4
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#define MT6363_RG_LDO_VRFIO18_RC0_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC1_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC2_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC3_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC4_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC5_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC6_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC7_OP_CFG_ADDR 0x1BD5
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#define MT6363_RG_LDO_VRFIO18_RC8_OP_CFG_ADDR 0x1BD6
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#define MT6363_RG_LDO_VRFIO18_RC9_OP_CFG_ADDR 0x1BD6
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#define MT6363_RG_LDO_VRFIO18_RC10_OP_CFG_ADDR 0x1BD6
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#define MT6363_RG_LDO_VRFIO18_RC11_OP_CFG_ADDR 0x1BD6
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#define MT6363_RG_LDO_VRFIO18_RC12_OP_CFG_ADDR 0x1BD6
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#define MT6363_RG_LDO_VRFIO18_RC13_OP_CFG_ADDR 0x1BD6
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#define MT6363_RG_LDO_VRFIO18_HW0_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_HW1_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_HW2_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_HW3_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_HW4_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_HW5_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_HW6_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_SW_OP_CFG_ADDR 0x1BD7
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#define MT6363_RG_LDO_VRFIO18_RC0_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC1_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC2_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC3_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC4_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC5_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC6_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC7_OP_MODE_ADDR 0x1BD8
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#define MT6363_RG_LDO_VRFIO18_RC8_OP_MODE_ADDR 0x1BD9
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#define MT6363_RG_LDO_VRFIO18_RC9_OP_MODE_ADDR 0x1BD9
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#define MT6363_RG_LDO_VRFIO18_RC10_OP_MODE_ADDR 0x1BD9
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#define MT6363_RG_LDO_VRFIO18_RC11_OP_MODE_ADDR 0x1BD9
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#define MT6363_RG_LDO_VRFIO18_RC12_OP_MODE_ADDR 0x1BD9
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#define MT6363_RG_LDO_VRFIO18_RC13_OP_MODE_ADDR 0x1BD9
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#define MT6363_RG_LDO_VRFIO18_HW0_OP_MODE_ADDR 0x1BDA
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#define MT6363_RG_LDO_VRFIO18_HW1_OP_MODE_ADDR 0x1BDA
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#define MT6363_RG_LDO_VRFIO18_HW2_OP_MODE_ADDR 0x1BDA
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#define MT6363_RG_LDO_VRFIO18_HW3_OP_MODE_ADDR 0x1BDA
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#define MT6363_RG_LDO_VRFIO18_HW4_OP_MODE_ADDR 0x1BDA
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#define MT6363_RG_LDO_VRFIO18_HW5_OP_MODE_ADDR 0x1BDA
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#define MT6363_RG_LDO_VRFIO18_HW6_OP_MODE_ADDR 0x1BDA
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#define MT6363_RG_LDO_VTREF18_ONLV_EN_ADDR 0x1C08
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#define MT6363_RG_LDO_VTREF18_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VTREF18_RC0_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC1_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC2_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC3_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC4_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC5_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC6_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC7_OP_EN_ADDR 0x1C0C
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#define MT6363_RG_LDO_VTREF18_RC8_OP_EN_ADDR 0x1C0D
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#define MT6363_RG_LDO_VTREF18_RC9_OP_EN_ADDR 0x1C0D
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#define MT6363_RG_LDO_VTREF18_RC10_OP_EN_ADDR 0x1C0D
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#define MT6363_RG_LDO_VTREF18_RC11_OP_EN_ADDR 0x1C0D
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#define MT6363_RG_LDO_VTREF18_RC12_OP_EN_ADDR 0x1C0D
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#define MT6363_RG_LDO_VTREF18_RC13_OP_EN_ADDR 0x1C0D
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#define MT6363_RG_LDO_VTREF18_HW0_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_HW1_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_HW2_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_HW3_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_HW4_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_HW5_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_HW6_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_SW_OP_EN_ADDR 0x1C0E
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#define MT6363_RG_LDO_VTREF18_RC0_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC1_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC2_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC3_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC4_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC5_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC6_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC7_OP_CFG_ADDR 0x1C0F
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#define MT6363_RG_LDO_VTREF18_RC8_OP_CFG_ADDR 0x1C10
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#define MT6363_RG_LDO_VTREF18_RC9_OP_CFG_ADDR 0x1C10
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#define MT6363_RG_LDO_VTREF18_RC10_OP_CFG_ADDR 0x1C10
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#define MT6363_RG_LDO_VTREF18_RC11_OP_CFG_ADDR 0x1C10
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#define MT6363_RG_LDO_VTREF18_RC12_OP_CFG_ADDR 0x1C10
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#define MT6363_RG_LDO_VTREF18_RC13_OP_CFG_ADDR 0x1C10
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#define MT6363_RG_LDO_VTREF18_HW0_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_HW1_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_HW2_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_HW3_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_HW4_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_HW5_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_HW6_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_SW_OP_CFG_ADDR 0x1C11
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#define MT6363_RG_LDO_VTREF18_RC0_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC1_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC2_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC3_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC4_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC5_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC6_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC7_OP_MODE_ADDR 0x1C12
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#define MT6363_RG_LDO_VTREF18_RC8_OP_MODE_ADDR 0x1C13
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#define MT6363_RG_LDO_VTREF18_RC9_OP_MODE_ADDR 0x1C13
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#define MT6363_RG_LDO_VTREF18_RC10_OP_MODE_ADDR 0x1C13
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#define MT6363_RG_LDO_VTREF18_RC11_OP_MODE_ADDR 0x1C13
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#define MT6363_RG_LDO_VTREF18_RC12_OP_MODE_ADDR 0x1C13
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#define MT6363_RG_LDO_VTREF18_RC13_OP_MODE_ADDR 0x1C13
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#define MT6363_RG_LDO_VTREF18_HW0_OP_MODE_ADDR 0x1C14
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#define MT6363_RG_LDO_VTREF18_HW1_OP_MODE_ADDR 0x1C14
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#define MT6363_RG_LDO_VTREF18_HW2_OP_MODE_ADDR 0x1C14
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#define MT6363_RG_LDO_VTREF18_HW3_OP_MODE_ADDR 0x1C14
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#define MT6363_RG_LDO_VTREF18_HW4_OP_MODE_ADDR 0x1C14
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#define MT6363_RG_LDO_VTREF18_HW5_OP_MODE_ADDR 0x1C14
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#define MT6363_RG_LDO_VTREF18_HW6_OP_MODE_ADDR 0x1C14
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#define MT6363_RG_LDO_VAUX18_ONLV_EN_ADDR 0x1C16
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#define MT6363_RG_LDO_VAUX18_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VAUX18_RC0_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC1_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC2_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC3_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC4_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC5_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC6_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC7_OP_EN_ADDR 0x1C1A
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#define MT6363_RG_LDO_VAUX18_RC8_OP_EN_ADDR 0x1C1B
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#define MT6363_RG_LDO_VAUX18_RC9_OP_EN_ADDR 0x1C1B
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#define MT6363_RG_LDO_VAUX18_RC10_OP_EN_ADDR 0x1C1B
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#define MT6363_RG_LDO_VAUX18_RC11_OP_EN_ADDR 0x1C1B
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#define MT6363_RG_LDO_VAUX18_RC12_OP_EN_ADDR 0x1C1B
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#define MT6363_RG_LDO_VAUX18_RC13_OP_EN_ADDR 0x1C1B
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#define MT6363_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1C1C
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#define MT6363_RG_LDO_VAUX18_RC0_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC1_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC2_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC3_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC4_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC5_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC6_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC7_OP_CFG_ADDR 0x1C1D
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#define MT6363_RG_LDO_VAUX18_RC8_OP_CFG_ADDR 0x1C1E
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#define MT6363_RG_LDO_VAUX18_RC9_OP_CFG_ADDR 0x1C1E
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#define MT6363_RG_LDO_VAUX18_RC10_OP_CFG_ADDR 0x1C1E
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|
#define MT6363_RG_LDO_VAUX18_RC11_OP_CFG_ADDR 0x1C1E
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#define MT6363_RG_LDO_VAUX18_RC12_OP_CFG_ADDR 0x1C1E
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#define MT6363_RG_LDO_VAUX18_RC13_OP_CFG_ADDR 0x1C1E
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|
#define MT6363_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1C1F
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|
#define MT6363_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1C1F
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#define MT6363_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1C1F
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#define MT6363_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1C1F
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#define MT6363_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1C1F
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#define MT6363_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1C1F
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|
#define MT6363_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1C1F
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#define MT6363_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1C1F
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|
#define MT6363_RG_LDO_VAUX18_RC0_OP_MODE_ADDR 0x1C20
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|
#define MT6363_RG_LDO_VAUX18_RC1_OP_MODE_ADDR 0x1C20
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|
#define MT6363_RG_LDO_VAUX18_RC2_OP_MODE_ADDR 0x1C20
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|
#define MT6363_RG_LDO_VAUX18_RC3_OP_MODE_ADDR 0x1C20
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|
#define MT6363_RG_LDO_VAUX18_RC4_OP_MODE_ADDR 0x1C20
|
|
#define MT6363_RG_LDO_VAUX18_RC5_OP_MODE_ADDR 0x1C20
|
|
#define MT6363_RG_LDO_VAUX18_RC6_OP_MODE_ADDR 0x1C20
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|
#define MT6363_RG_LDO_VAUX18_RC7_OP_MODE_ADDR 0x1C20
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|
#define MT6363_RG_LDO_VAUX18_RC8_OP_MODE_ADDR 0x1C21
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|
#define MT6363_RG_LDO_VAUX18_RC9_OP_MODE_ADDR 0x1C21
|
|
#define MT6363_RG_LDO_VAUX18_RC10_OP_MODE_ADDR 0x1C21
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|
#define MT6363_RG_LDO_VAUX18_RC11_OP_MODE_ADDR 0x1C21
|
|
#define MT6363_RG_LDO_VAUX18_RC12_OP_MODE_ADDR 0x1C21
|
|
#define MT6363_RG_LDO_VAUX18_RC13_OP_MODE_ADDR 0x1C21
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|
#define MT6363_RG_LDO_VAUX18_HW0_OP_MODE_ADDR 0x1C22
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|
#define MT6363_RG_LDO_VAUX18_HW1_OP_MODE_ADDR 0x1C22
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|
#define MT6363_RG_LDO_VAUX18_HW2_OP_MODE_ADDR 0x1C22
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|
#define MT6363_RG_LDO_VAUX18_HW3_OP_MODE_ADDR 0x1C22
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|
#define MT6363_RG_LDO_VAUX18_HW4_OP_MODE_ADDR 0x1C22
|
|
#define MT6363_RG_LDO_VAUX18_HW5_OP_MODE_ADDR 0x1C22
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|
#define MT6363_RG_LDO_VAUX18_HW6_OP_MODE_ADDR 0x1C22
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|
#define MT6363_RG_LDO_VEMC_ONLV_EN_ADDR 0x1C24
|
|
#define MT6363_RG_LDO_VEMC_ONLV_EN_SHIFT 3
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|
#define MT6363_RG_LDO_VEMC_RC0_OP_EN_ADDR 0x1C28
|
|
#define MT6363_RG_LDO_VEMC_RC1_OP_EN_ADDR 0x1C28
|
|
#define MT6363_RG_LDO_VEMC_RC2_OP_EN_ADDR 0x1C28
|
|
#define MT6363_RG_LDO_VEMC_RC3_OP_EN_ADDR 0x1C28
|
|
#define MT6363_RG_LDO_VEMC_RC4_OP_EN_ADDR 0x1C28
|
|
#define MT6363_RG_LDO_VEMC_RC5_OP_EN_ADDR 0x1C28
|
|
#define MT6363_RG_LDO_VEMC_RC6_OP_EN_ADDR 0x1C28
|
|
#define MT6363_RG_LDO_VEMC_RC7_OP_EN_ADDR 0x1C28
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#define MT6363_RG_LDO_VEMC_RC8_OP_EN_ADDR 0x1C29
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#define MT6363_RG_LDO_VEMC_RC9_OP_EN_ADDR 0x1C29
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#define MT6363_RG_LDO_VEMC_RC10_OP_EN_ADDR 0x1C29
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#define MT6363_RG_LDO_VEMC_RC11_OP_EN_ADDR 0x1C29
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#define MT6363_RG_LDO_VEMC_RC12_OP_EN_ADDR 0x1C29
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#define MT6363_RG_LDO_VEMC_RC13_OP_EN_ADDR 0x1C29
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#define MT6363_RG_LDO_VEMC_HW0_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_HW1_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_HW2_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_HW3_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_HW4_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_HW5_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_HW6_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_SW_OP_EN_ADDR 0x1C2A
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#define MT6363_RG_LDO_VEMC_RC0_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC1_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC2_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC3_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC4_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC5_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC6_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC7_OP_CFG_ADDR 0x1C2B
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#define MT6363_RG_LDO_VEMC_RC8_OP_CFG_ADDR 0x1C2C
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#define MT6363_RG_LDO_VEMC_RC9_OP_CFG_ADDR 0x1C2C
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#define MT6363_RG_LDO_VEMC_RC10_OP_CFG_ADDR 0x1C2C
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#define MT6363_RG_LDO_VEMC_RC11_OP_CFG_ADDR 0x1C2C
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#define MT6363_RG_LDO_VEMC_RC12_OP_CFG_ADDR 0x1C2C
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#define MT6363_RG_LDO_VEMC_RC13_OP_CFG_ADDR 0x1C2C
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#define MT6363_RG_LDO_VEMC_HW0_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_HW1_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_HW2_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_HW3_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_HW4_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_HW5_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_HW6_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_SW_OP_CFG_ADDR 0x1C2D
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#define MT6363_RG_LDO_VEMC_RC0_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC1_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC2_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC3_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC4_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC5_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC6_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC7_OP_MODE_ADDR 0x1C2E
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#define MT6363_RG_LDO_VEMC_RC8_OP_MODE_ADDR 0x1C2F
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#define MT6363_RG_LDO_VEMC_RC9_OP_MODE_ADDR 0x1C2F
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#define MT6363_RG_LDO_VEMC_RC10_OP_MODE_ADDR 0x1C2F
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#define MT6363_RG_LDO_VEMC_RC11_OP_MODE_ADDR 0x1C2F
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#define MT6363_RG_LDO_VEMC_RC12_OP_MODE_ADDR 0x1C2F
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#define MT6363_RG_LDO_VEMC_RC13_OP_MODE_ADDR 0x1C2F
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#define MT6363_RG_LDO_VEMC_HW0_OP_MODE_ADDR 0x1C30
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#define MT6363_RG_LDO_VEMC_HW1_OP_MODE_ADDR 0x1C30
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#define MT6363_RG_LDO_VEMC_HW2_OP_MODE_ADDR 0x1C30
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#define MT6363_RG_LDO_VEMC_HW3_OP_MODE_ADDR 0x1C30
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#define MT6363_RG_LDO_VEMC_HW4_OP_MODE_ADDR 0x1C30
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#define MT6363_RG_LDO_VEMC_HW5_OP_MODE_ADDR 0x1C30
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#define MT6363_RG_LDO_VEMC_HW6_OP_MODE_ADDR 0x1C30
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#define MT6363_RG_LDO_VUFS12_ONLV_EN_ADDR 0x1C32
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#define MT6363_RG_LDO_VUFS12_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VUFS12_RC0_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC1_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC2_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC3_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC4_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC5_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC6_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC7_OP_EN_ADDR 0x1C36
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#define MT6363_RG_LDO_VUFS12_RC8_OP_EN_ADDR 0x1C37
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#define MT6363_RG_LDO_VUFS12_RC9_OP_EN_ADDR 0x1C37
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#define MT6363_RG_LDO_VUFS12_RC10_OP_EN_ADDR 0x1C37
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#define MT6363_RG_LDO_VUFS12_RC11_OP_EN_ADDR 0x1C37
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#define MT6363_RG_LDO_VUFS12_RC12_OP_EN_ADDR 0x1C37
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#define MT6363_RG_LDO_VUFS12_RC13_OP_EN_ADDR 0x1C37
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#define MT6363_RG_LDO_VUFS12_HW0_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_HW1_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_HW2_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_HW3_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_HW4_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_HW5_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_HW6_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_SW_OP_EN_ADDR 0x1C38
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#define MT6363_RG_LDO_VUFS12_RC0_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC1_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC2_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC3_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC4_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC5_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC6_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC7_OP_CFG_ADDR 0x1C39
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#define MT6363_RG_LDO_VUFS12_RC8_OP_CFG_ADDR 0x1C3A
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#define MT6363_RG_LDO_VUFS12_RC9_OP_CFG_ADDR 0x1C3A
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#define MT6363_RG_LDO_VUFS12_RC10_OP_CFG_ADDR 0x1C3A
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#define MT6363_RG_LDO_VUFS12_RC11_OP_CFG_ADDR 0x1C3A
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#define MT6363_RG_LDO_VUFS12_RC12_OP_CFG_ADDR 0x1C3A
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#define MT6363_RG_LDO_VUFS12_RC13_OP_CFG_ADDR 0x1C3A
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#define MT6363_RG_LDO_VUFS12_HW0_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_HW1_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_HW2_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_HW3_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_HW4_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_HW5_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_HW6_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_SW_OP_CFG_ADDR 0x1C3B
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#define MT6363_RG_LDO_VUFS12_RC0_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC1_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC2_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC3_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC4_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC5_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC6_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC7_OP_MODE_ADDR 0x1C3C
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#define MT6363_RG_LDO_VUFS12_RC8_OP_MODE_ADDR 0x1C3D
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#define MT6363_RG_LDO_VUFS12_RC9_OP_MODE_ADDR 0x1C3D
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#define MT6363_RG_LDO_VUFS12_RC10_OP_MODE_ADDR 0x1C3D
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#define MT6363_RG_LDO_VUFS12_RC11_OP_MODE_ADDR 0x1C3D
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#define MT6363_RG_LDO_VUFS12_RC12_OP_MODE_ADDR 0x1C3D
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#define MT6363_RG_LDO_VUFS12_RC13_OP_MODE_ADDR 0x1C3D
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#define MT6363_RG_LDO_VUFS12_HW0_OP_MODE_ADDR 0x1C3E
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#define MT6363_RG_LDO_VUFS12_HW1_OP_MODE_ADDR 0x1C3E
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#define MT6363_RG_LDO_VUFS12_HW2_OP_MODE_ADDR 0x1C3E
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#define MT6363_RG_LDO_VUFS12_HW3_OP_MODE_ADDR 0x1C3E
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#define MT6363_RG_LDO_VUFS12_HW4_OP_MODE_ADDR 0x1C3E
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#define MT6363_RG_LDO_VUFS12_HW5_OP_MODE_ADDR 0x1C3E
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#define MT6363_RG_LDO_VUFS12_HW6_OP_MODE_ADDR 0x1C3E
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#define MT6363_RG_LDO_VUFS18_ONLV_EN_ADDR 0x1C40
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#define MT6363_RG_LDO_VUFS18_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VUFS18_RC0_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC1_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC2_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC3_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC4_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC5_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC6_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC7_OP_EN_ADDR 0x1C44
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#define MT6363_RG_LDO_VUFS18_RC8_OP_EN_ADDR 0x1C45
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#define MT6363_RG_LDO_VUFS18_RC9_OP_EN_ADDR 0x1C45
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#define MT6363_RG_LDO_VUFS18_RC10_OP_EN_ADDR 0x1C45
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#define MT6363_RG_LDO_VUFS18_RC11_OP_EN_ADDR 0x1C45
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#define MT6363_RG_LDO_VUFS18_RC12_OP_EN_ADDR 0x1C45
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#define MT6363_RG_LDO_VUFS18_RC13_OP_EN_ADDR 0x1C45
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#define MT6363_RG_LDO_VUFS18_HW0_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_HW1_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_HW2_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_HW3_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_HW4_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_HW5_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_HW6_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_SW_OP_EN_ADDR 0x1C46
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#define MT6363_RG_LDO_VUFS18_RC0_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC1_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC2_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC3_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC4_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC5_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC6_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC7_OP_CFG_ADDR 0x1C47
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#define MT6363_RG_LDO_VUFS18_RC8_OP_CFG_ADDR 0x1C48
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#define MT6363_RG_LDO_VUFS18_RC9_OP_CFG_ADDR 0x1C48
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#define MT6363_RG_LDO_VUFS18_RC10_OP_CFG_ADDR 0x1C48
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#define MT6363_RG_LDO_VUFS18_RC11_OP_CFG_ADDR 0x1C48
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#define MT6363_RG_LDO_VUFS18_RC12_OP_CFG_ADDR 0x1C48
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#define MT6363_RG_LDO_VUFS18_RC13_OP_CFG_ADDR 0x1C48
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#define MT6363_RG_LDO_VUFS18_HW0_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_HW1_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_HW2_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_HW3_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_HW4_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_HW5_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_HW6_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_SW_OP_CFG_ADDR 0x1C49
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#define MT6363_RG_LDO_VUFS18_RC0_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC1_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC2_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC3_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC4_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC5_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC6_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC7_OP_MODE_ADDR 0x1C4A
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#define MT6363_RG_LDO_VUFS18_RC8_OP_MODE_ADDR 0x1C4B
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|
#define MT6363_RG_LDO_VUFS18_RC9_OP_MODE_ADDR 0x1C4B
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|
#define MT6363_RG_LDO_VUFS18_RC10_OP_MODE_ADDR 0x1C4B
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|
#define MT6363_RG_LDO_VUFS18_RC11_OP_MODE_ADDR 0x1C4B
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|
#define MT6363_RG_LDO_VUFS18_RC12_OP_MODE_ADDR 0x1C4B
|
|
#define MT6363_RG_LDO_VUFS18_RC13_OP_MODE_ADDR 0x1C4B
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|
#define MT6363_RG_LDO_VUFS18_HW0_OP_MODE_ADDR 0x1C4C
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|
#define MT6363_RG_LDO_VUFS18_HW1_OP_MODE_ADDR 0x1C4C
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|
#define MT6363_RG_LDO_VUFS18_HW2_OP_MODE_ADDR 0x1C4C
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|
#define MT6363_RG_LDO_VUFS18_HW3_OP_MODE_ADDR 0x1C4C
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|
#define MT6363_RG_LDO_VUFS18_HW4_OP_MODE_ADDR 0x1C4C
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|
#define MT6363_RG_LDO_VUFS18_HW5_OP_MODE_ADDR 0x1C4C
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|
#define MT6363_RG_LDO_VUFS18_HW6_OP_MODE_ADDR 0x1C4C
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|
#define MT6363_RG_LDO_VIO18_ONLV_EN_ADDR 0x1C4E
|
|
#define MT6363_RG_LDO_VIO18_ONLV_EN_SHIFT 3
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|
#define MT6363_RG_LDO_VIO18_RC0_OP_EN_ADDR 0x1C52
|
|
#define MT6363_RG_LDO_VIO18_RC1_OP_EN_ADDR 0x1C52
|
|
#define MT6363_RG_LDO_VIO18_RC2_OP_EN_ADDR 0x1C52
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|
#define MT6363_RG_LDO_VIO18_RC3_OP_EN_ADDR 0x1C52
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|
#define MT6363_RG_LDO_VIO18_RC4_OP_EN_ADDR 0x1C52
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|
#define MT6363_RG_LDO_VIO18_RC5_OP_EN_ADDR 0x1C52
|
|
#define MT6363_RG_LDO_VIO18_RC6_OP_EN_ADDR 0x1C52
|
|
#define MT6363_RG_LDO_VIO18_RC7_OP_EN_ADDR 0x1C52
|
|
#define MT6363_RG_LDO_VIO18_RC8_OP_EN_ADDR 0x1C53
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|
#define MT6363_RG_LDO_VIO18_RC9_OP_EN_ADDR 0x1C53
|
|
#define MT6363_RG_LDO_VIO18_RC10_OP_EN_ADDR 0x1C53
|
|
#define MT6363_RG_LDO_VIO18_RC11_OP_EN_ADDR 0x1C53
|
|
#define MT6363_RG_LDO_VIO18_RC12_OP_EN_ADDR 0x1C53
|
|
#define MT6363_RG_LDO_VIO18_RC13_OP_EN_ADDR 0x1C53
|
|
#define MT6363_RG_LDO_VIO18_HW0_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_HW1_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_HW2_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_HW3_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_HW4_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_HW5_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_HW6_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_SW_OP_EN_ADDR 0x1C54
|
|
#define MT6363_RG_LDO_VIO18_RC0_OP_CFG_ADDR 0x1C55
|
|
#define MT6363_RG_LDO_VIO18_RC1_OP_CFG_ADDR 0x1C55
|
|
#define MT6363_RG_LDO_VIO18_RC2_OP_CFG_ADDR 0x1C55
|
|
#define MT6363_RG_LDO_VIO18_RC3_OP_CFG_ADDR 0x1C55
|
|
#define MT6363_RG_LDO_VIO18_RC4_OP_CFG_ADDR 0x1C55
|
|
#define MT6363_RG_LDO_VIO18_RC5_OP_CFG_ADDR 0x1C55
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#define MT6363_RG_LDO_VIO18_RC6_OP_CFG_ADDR 0x1C55
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#define MT6363_RG_LDO_VIO18_RC7_OP_CFG_ADDR 0x1C55
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#define MT6363_RG_LDO_VIO18_RC8_OP_CFG_ADDR 0x1C56
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#define MT6363_RG_LDO_VIO18_RC9_OP_CFG_ADDR 0x1C56
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#define MT6363_RG_LDO_VIO18_RC10_OP_CFG_ADDR 0x1C56
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#define MT6363_RG_LDO_VIO18_RC11_OP_CFG_ADDR 0x1C56
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#define MT6363_RG_LDO_VIO18_RC12_OP_CFG_ADDR 0x1C56
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#define MT6363_RG_LDO_VIO18_RC13_OP_CFG_ADDR 0x1C56
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#define MT6363_RG_LDO_VIO18_HW0_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_HW1_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_HW2_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_HW3_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_HW4_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_HW5_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_HW6_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_SW_OP_CFG_ADDR 0x1C57
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#define MT6363_RG_LDO_VIO18_RC0_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC1_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC2_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC3_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC4_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC5_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC6_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC7_OP_MODE_ADDR 0x1C58
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#define MT6363_RG_LDO_VIO18_RC8_OP_MODE_ADDR 0x1C59
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#define MT6363_RG_LDO_VIO18_RC9_OP_MODE_ADDR 0x1C59
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#define MT6363_RG_LDO_VIO18_RC10_OP_MODE_ADDR 0x1C59
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#define MT6363_RG_LDO_VIO18_RC11_OP_MODE_ADDR 0x1C59
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#define MT6363_RG_LDO_VIO18_RC12_OP_MODE_ADDR 0x1C59
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#define MT6363_RG_LDO_VIO18_RC13_OP_MODE_ADDR 0x1C59
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#define MT6363_RG_LDO_VIO18_HW0_OP_MODE_ADDR 0x1C5A
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#define MT6363_RG_LDO_VIO18_HW1_OP_MODE_ADDR 0x1C5A
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#define MT6363_RG_LDO_VIO18_HW2_OP_MODE_ADDR 0x1C5A
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#define MT6363_RG_LDO_VIO18_HW3_OP_MODE_ADDR 0x1C5A
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#define MT6363_RG_LDO_VIO18_HW4_OP_MODE_ADDR 0x1C5A
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#define MT6363_RG_LDO_VIO18_HW5_OP_MODE_ADDR 0x1C5A
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#define MT6363_RG_LDO_VIO18_HW6_OP_MODE_ADDR 0x1C5A
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#define MT6363_RG_LDO_VIO075_ONLV_EN_ADDR 0x1C88
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#define MT6363_RG_LDO_VIO075_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VIO075_RC0_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC1_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC2_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC3_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC4_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC5_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC6_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC7_OP_EN_ADDR 0x1C8C
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#define MT6363_RG_LDO_VIO075_RC8_OP_EN_ADDR 0x1C8D
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#define MT6363_RG_LDO_VIO075_RC9_OP_EN_ADDR 0x1C8D
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#define MT6363_RG_LDO_VIO075_RC10_OP_EN_ADDR 0x1C8D
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#define MT6363_RG_LDO_VIO075_RC11_OP_EN_ADDR 0x1C8D
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#define MT6363_RG_LDO_VIO075_RC12_OP_EN_ADDR 0x1C8D
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#define MT6363_RG_LDO_VIO075_RC13_OP_EN_ADDR 0x1C8D
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#define MT6363_RG_LDO_VIO075_HW0_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_HW1_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_HW2_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_HW3_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_HW4_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_HW5_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_HW6_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_SW_OP_EN_ADDR 0x1C8E
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#define MT6363_RG_LDO_VIO075_RC0_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC1_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC2_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC3_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC4_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC5_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC6_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC7_OP_CFG_ADDR 0x1C8F
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#define MT6363_RG_LDO_VIO075_RC8_OP_CFG_ADDR 0x1C90
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#define MT6363_RG_LDO_VIO075_RC9_OP_CFG_ADDR 0x1C90
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#define MT6363_RG_LDO_VIO075_RC10_OP_CFG_ADDR 0x1C90
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#define MT6363_RG_LDO_VIO075_RC11_OP_CFG_ADDR 0x1C90
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#define MT6363_RG_LDO_VIO075_RC12_OP_CFG_ADDR 0x1C90
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#define MT6363_RG_LDO_VIO075_RC13_OP_CFG_ADDR 0x1C90
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#define MT6363_RG_LDO_VIO075_HW0_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_HW1_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_HW2_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_HW3_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_HW4_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_HW5_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_HW6_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_SW_OP_CFG_ADDR 0x1C91
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#define MT6363_RG_LDO_VIO075_RC0_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC1_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC2_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC3_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC4_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC5_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC6_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC7_OP_MODE_ADDR 0x1C92
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#define MT6363_RG_LDO_VIO075_RC8_OP_MODE_ADDR 0x1C93
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#define MT6363_RG_LDO_VIO075_RC9_OP_MODE_ADDR 0x1C93
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#define MT6363_RG_LDO_VIO075_RC10_OP_MODE_ADDR 0x1C93
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#define MT6363_RG_LDO_VIO075_RC11_OP_MODE_ADDR 0x1C93
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#define MT6363_RG_LDO_VIO075_RC12_OP_MODE_ADDR 0x1C93
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#define MT6363_RG_LDO_VIO075_RC13_OP_MODE_ADDR 0x1C93
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#define MT6363_RG_LDO_VIO075_HW0_OP_MODE_ADDR 0x1C94
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#define MT6363_RG_LDO_VIO075_HW1_OP_MODE_ADDR 0x1C94
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#define MT6363_RG_LDO_VIO075_HW2_OP_MODE_ADDR 0x1C94
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#define MT6363_RG_LDO_VIO075_HW3_OP_MODE_ADDR 0x1C94
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#define MT6363_RG_LDO_VIO075_HW4_OP_MODE_ADDR 0x1C94
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#define MT6363_RG_LDO_VIO075_HW5_OP_MODE_ADDR 0x1C94
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#define MT6363_RG_LDO_VIO075_HW6_OP_MODE_ADDR 0x1C94
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#define MT6363_RG_LDO_VA12_1_ONLV_EN_ADDR 0x1C96
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#define MT6363_RG_LDO_VA12_1_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VA12_1_RC0_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC1_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC2_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC3_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC4_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC5_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC6_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC7_OP_EN_ADDR 0x1C9A
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#define MT6363_RG_LDO_VA12_1_RC8_OP_EN_ADDR 0x1C9B
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#define MT6363_RG_LDO_VA12_1_RC9_OP_EN_ADDR 0x1C9B
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#define MT6363_RG_LDO_VA12_1_RC10_OP_EN_ADDR 0x1C9B
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#define MT6363_RG_LDO_VA12_1_RC11_OP_EN_ADDR 0x1C9B
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#define MT6363_RG_LDO_VA12_1_RC12_OP_EN_ADDR 0x1C9B
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#define MT6363_RG_LDO_VA12_1_RC13_OP_EN_ADDR 0x1C9B
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#define MT6363_RG_LDO_VA12_1_HW0_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_HW1_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_HW2_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_HW3_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_HW4_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_HW5_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_HW6_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_SW_OP_EN_ADDR 0x1C9C
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#define MT6363_RG_LDO_VA12_1_RC0_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC1_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC2_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC3_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC4_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC5_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC6_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC7_OP_CFG_ADDR 0x1C9D
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#define MT6363_RG_LDO_VA12_1_RC8_OP_CFG_ADDR 0x1C9E
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#define MT6363_RG_LDO_VA12_1_RC9_OP_CFG_ADDR 0x1C9E
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#define MT6363_RG_LDO_VA12_1_RC10_OP_CFG_ADDR 0x1C9E
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#define MT6363_RG_LDO_VA12_1_RC11_OP_CFG_ADDR 0x1C9E
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#define MT6363_RG_LDO_VA12_1_RC12_OP_CFG_ADDR 0x1C9E
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#define MT6363_RG_LDO_VA12_1_RC13_OP_CFG_ADDR 0x1C9E
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#define MT6363_RG_LDO_VA12_1_HW0_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_HW1_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_HW2_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_HW3_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_HW4_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_HW5_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_HW6_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_SW_OP_CFG_ADDR 0x1C9F
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#define MT6363_RG_LDO_VA12_1_RC0_OP_MODE_ADDR 0x1CA0
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#define MT6363_RG_LDO_VA12_1_RC1_OP_MODE_ADDR 0x1CA0
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|
#define MT6363_RG_LDO_VA12_1_RC2_OP_MODE_ADDR 0x1CA0
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|
#define MT6363_RG_LDO_VA12_1_RC3_OP_MODE_ADDR 0x1CA0
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|
#define MT6363_RG_LDO_VA12_1_RC4_OP_MODE_ADDR 0x1CA0
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|
#define MT6363_RG_LDO_VA12_1_RC5_OP_MODE_ADDR 0x1CA0
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|
#define MT6363_RG_LDO_VA12_1_RC6_OP_MODE_ADDR 0x1CA0
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|
#define MT6363_RG_LDO_VA12_1_RC7_OP_MODE_ADDR 0x1CA0
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|
#define MT6363_RG_LDO_VA12_1_RC8_OP_MODE_ADDR 0x1CA1
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|
#define MT6363_RG_LDO_VA12_1_RC9_OP_MODE_ADDR 0x1CA1
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|
#define MT6363_RG_LDO_VA12_1_RC10_OP_MODE_ADDR 0x1CA1
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|
#define MT6363_RG_LDO_VA12_1_RC11_OP_MODE_ADDR 0x1CA1
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|
#define MT6363_RG_LDO_VA12_1_RC12_OP_MODE_ADDR 0x1CA1
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#define MT6363_RG_LDO_VA12_1_RC13_OP_MODE_ADDR 0x1CA1
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|
#define MT6363_RG_LDO_VA12_1_HW0_OP_MODE_ADDR 0x1CA2
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|
#define MT6363_RG_LDO_VA12_1_HW1_OP_MODE_ADDR 0x1CA2
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|
#define MT6363_RG_LDO_VA12_1_HW2_OP_MODE_ADDR 0x1CA2
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|
#define MT6363_RG_LDO_VA12_1_HW3_OP_MODE_ADDR 0x1CA2
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|
#define MT6363_RG_LDO_VA12_1_HW4_OP_MODE_ADDR 0x1CA2
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|
#define MT6363_RG_LDO_VA12_1_HW5_OP_MODE_ADDR 0x1CA2
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|
#define MT6363_RG_LDO_VA12_1_HW6_OP_MODE_ADDR 0x1CA2
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|
#define MT6363_RG_LDO_VA12_2_ONLV_EN_ADDR 0x1CA4
|
|
#define MT6363_RG_LDO_VA12_2_ONLV_EN_SHIFT 3
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|
#define MT6363_RG_LDO_VA12_2_RC0_OP_EN_ADDR 0x1CA8
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|
#define MT6363_RG_LDO_VA12_2_RC1_OP_EN_ADDR 0x1CA8
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|
#define MT6363_RG_LDO_VA12_2_RC2_OP_EN_ADDR 0x1CA8
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|
#define MT6363_RG_LDO_VA12_2_RC3_OP_EN_ADDR 0x1CA8
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|
#define MT6363_RG_LDO_VA12_2_RC4_OP_EN_ADDR 0x1CA8
|
|
#define MT6363_RG_LDO_VA12_2_RC5_OP_EN_ADDR 0x1CA8
|
|
#define MT6363_RG_LDO_VA12_2_RC6_OP_EN_ADDR 0x1CA8
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|
#define MT6363_RG_LDO_VA12_2_RC7_OP_EN_ADDR 0x1CA8
|
|
#define MT6363_RG_LDO_VA12_2_RC8_OP_EN_ADDR 0x1CA9
|
|
#define MT6363_RG_LDO_VA12_2_RC9_OP_EN_ADDR 0x1CA9
|
|
#define MT6363_RG_LDO_VA12_2_RC10_OP_EN_ADDR 0x1CA9
|
|
#define MT6363_RG_LDO_VA12_2_RC11_OP_EN_ADDR 0x1CA9
|
|
#define MT6363_RG_LDO_VA12_2_RC12_OP_EN_ADDR 0x1CA9
|
|
#define MT6363_RG_LDO_VA12_2_RC13_OP_EN_ADDR 0x1CA9
|
|
#define MT6363_RG_LDO_VA12_2_HW0_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_HW1_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_HW2_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_HW3_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_HW4_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_HW5_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_HW6_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_SW_OP_EN_ADDR 0x1CAA
|
|
#define MT6363_RG_LDO_VA12_2_RC0_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC1_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC2_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC3_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC4_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC5_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC6_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC7_OP_CFG_ADDR 0x1CAB
|
|
#define MT6363_RG_LDO_VA12_2_RC8_OP_CFG_ADDR 0x1CAC
|
|
#define MT6363_RG_LDO_VA12_2_RC9_OP_CFG_ADDR 0x1CAC
|
|
#define MT6363_RG_LDO_VA12_2_RC10_OP_CFG_ADDR 0x1CAC
|
|
#define MT6363_RG_LDO_VA12_2_RC11_OP_CFG_ADDR 0x1CAC
|
|
#define MT6363_RG_LDO_VA12_2_RC12_OP_CFG_ADDR 0x1CAC
|
|
#define MT6363_RG_LDO_VA12_2_RC13_OP_CFG_ADDR 0x1CAC
|
|
#define MT6363_RG_LDO_VA12_2_HW0_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_HW1_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_HW2_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_HW3_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_HW4_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_HW5_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_HW6_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_SW_OP_CFG_ADDR 0x1CAD
|
|
#define MT6363_RG_LDO_VA12_2_RC0_OP_MODE_ADDR 0x1CAE
|
|
#define MT6363_RG_LDO_VA12_2_RC1_OP_MODE_ADDR 0x1CAE
|
|
#define MT6363_RG_LDO_VA12_2_RC2_OP_MODE_ADDR 0x1CAE
|
|
#define MT6363_RG_LDO_VA12_2_RC3_OP_MODE_ADDR 0x1CAE
|
|
#define MT6363_RG_LDO_VA12_2_RC4_OP_MODE_ADDR 0x1CAE
|
|
#define MT6363_RG_LDO_VA12_2_RC5_OP_MODE_ADDR 0x1CAE
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#define MT6363_RG_LDO_VA12_2_RC6_OP_MODE_ADDR 0x1CAE
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#define MT6363_RG_LDO_VA12_2_RC7_OP_MODE_ADDR 0x1CAE
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#define MT6363_RG_LDO_VA12_2_RC8_OP_MODE_ADDR 0x1CAF
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#define MT6363_RG_LDO_VA12_2_RC9_OP_MODE_ADDR 0x1CAF
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#define MT6363_RG_LDO_VA12_2_RC10_OP_MODE_ADDR 0x1CAF
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#define MT6363_RG_LDO_VA12_2_RC11_OP_MODE_ADDR 0x1CAF
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#define MT6363_RG_LDO_VA12_2_RC12_OP_MODE_ADDR 0x1CAF
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#define MT6363_RG_LDO_VA12_2_RC13_OP_MODE_ADDR 0x1CAF
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#define MT6363_RG_LDO_VA12_2_HW0_OP_MODE_ADDR 0x1CB0
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#define MT6363_RG_LDO_VA12_2_HW1_OP_MODE_ADDR 0x1CB0
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#define MT6363_RG_LDO_VA12_2_HW2_OP_MODE_ADDR 0x1CB0
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#define MT6363_RG_LDO_VA12_2_HW3_OP_MODE_ADDR 0x1CB0
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#define MT6363_RG_LDO_VA12_2_HW4_OP_MODE_ADDR 0x1CB0
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#define MT6363_RG_LDO_VA12_2_HW5_OP_MODE_ADDR 0x1CB0
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#define MT6363_RG_LDO_VA12_2_HW6_OP_MODE_ADDR 0x1CB0
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#define MT6363_RG_LDO_VA15_ONLV_EN_ADDR 0x1CB2
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#define MT6363_RG_LDO_VA15_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VA15_RC0_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC1_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC2_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC3_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC4_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC5_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC6_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC7_OP_EN_ADDR 0x1CB6
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#define MT6363_RG_LDO_VA15_RC8_OP_EN_ADDR 0x1CB7
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#define MT6363_RG_LDO_VA15_RC9_OP_EN_ADDR 0x1CB7
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#define MT6363_RG_LDO_VA15_RC10_OP_EN_ADDR 0x1CB7
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#define MT6363_RG_LDO_VA15_RC11_OP_EN_ADDR 0x1CB7
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#define MT6363_RG_LDO_VA15_RC12_OP_EN_ADDR 0x1CB7
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#define MT6363_RG_LDO_VA15_RC13_OP_EN_ADDR 0x1CB7
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#define MT6363_RG_LDO_VA15_HW0_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_HW1_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_HW2_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_HW3_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_HW4_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_HW5_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_HW6_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_SW_OP_EN_ADDR 0x1CB8
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#define MT6363_RG_LDO_VA15_RC0_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC1_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC2_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC3_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC4_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC5_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC6_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC7_OP_CFG_ADDR 0x1CB9
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#define MT6363_RG_LDO_VA15_RC8_OP_CFG_ADDR 0x1CBA
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#define MT6363_RG_LDO_VA15_RC9_OP_CFG_ADDR 0x1CBA
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#define MT6363_RG_LDO_VA15_RC10_OP_CFG_ADDR 0x1CBA
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#define MT6363_RG_LDO_VA15_RC11_OP_CFG_ADDR 0x1CBA
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#define MT6363_RG_LDO_VA15_RC12_OP_CFG_ADDR 0x1CBA
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#define MT6363_RG_LDO_VA15_RC13_OP_CFG_ADDR 0x1CBA
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#define MT6363_RG_LDO_VA15_HW0_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_HW1_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_HW2_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_HW3_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_HW4_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_HW5_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_HW6_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_SW_OP_CFG_ADDR 0x1CBB
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#define MT6363_RG_LDO_VA15_RC0_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC1_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC2_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC3_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC4_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC5_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC6_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC7_OP_MODE_ADDR 0x1CBC
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#define MT6363_RG_LDO_VA15_RC8_OP_MODE_ADDR 0x1CBD
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#define MT6363_RG_LDO_VA15_RC9_OP_MODE_ADDR 0x1CBD
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#define MT6363_RG_LDO_VA15_RC10_OP_MODE_ADDR 0x1CBD
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#define MT6363_RG_LDO_VA15_RC11_OP_MODE_ADDR 0x1CBD
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#define MT6363_RG_LDO_VA15_RC12_OP_MODE_ADDR 0x1CBD
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#define MT6363_RG_LDO_VA15_RC13_OP_MODE_ADDR 0x1CBD
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#define MT6363_RG_LDO_VA15_HW0_OP_MODE_ADDR 0x1CBE
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#define MT6363_RG_LDO_VA15_HW1_OP_MODE_ADDR 0x1CBE
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#define MT6363_RG_LDO_VA15_HW2_OP_MODE_ADDR 0x1CBE
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#define MT6363_RG_LDO_VA15_HW3_OP_MODE_ADDR 0x1CBE
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#define MT6363_RG_LDO_VA15_HW4_OP_MODE_ADDR 0x1CBE
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#define MT6363_RG_LDO_VA15_HW5_OP_MODE_ADDR 0x1CBE
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#define MT6363_RG_LDO_VA15_HW6_OP_MODE_ADDR 0x1CBE
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#define MT6363_RG_LDO_VM18_ONLV_EN_ADDR 0x1CC0
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#define MT6363_RG_LDO_VM18_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VM18_RC0_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC1_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC2_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC3_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC4_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC5_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC6_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC7_OP_EN_ADDR 0x1CC4
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#define MT6363_RG_LDO_VM18_RC8_OP_EN_ADDR 0x1CC5
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#define MT6363_RG_LDO_VM18_RC9_OP_EN_ADDR 0x1CC5
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#define MT6363_RG_LDO_VM18_RC10_OP_EN_ADDR 0x1CC5
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#define MT6363_RG_LDO_VM18_RC11_OP_EN_ADDR 0x1CC5
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#define MT6363_RG_LDO_VM18_RC12_OP_EN_ADDR 0x1CC5
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#define MT6363_RG_LDO_VM18_RC13_OP_EN_ADDR 0x1CC5
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#define MT6363_RG_LDO_VM18_HW0_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_HW1_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_HW2_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_HW3_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_HW4_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_HW5_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_HW6_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_SW_OP_EN_ADDR 0x1CC6
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#define MT6363_RG_LDO_VM18_RC0_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC1_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC2_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC3_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC4_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC5_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC6_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC7_OP_CFG_ADDR 0x1CC7
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#define MT6363_RG_LDO_VM18_RC8_OP_CFG_ADDR 0x1CC8
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#define MT6363_RG_LDO_VM18_RC9_OP_CFG_ADDR 0x1CC8
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#define MT6363_RG_LDO_VM18_RC10_OP_CFG_ADDR 0x1CC8
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#define MT6363_RG_LDO_VM18_RC11_OP_CFG_ADDR 0x1CC8
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#define MT6363_RG_LDO_VM18_RC12_OP_CFG_ADDR 0x1CC8
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#define MT6363_RG_LDO_VM18_RC13_OP_CFG_ADDR 0x1CC8
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#define MT6363_RG_LDO_VM18_HW0_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_HW1_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_HW2_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_HW3_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_HW4_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_HW5_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_HW6_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_SW_OP_CFG_ADDR 0x1CC9
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#define MT6363_RG_LDO_VM18_RC0_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC1_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC2_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC3_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC4_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC5_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC6_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC7_OP_MODE_ADDR 0x1CCA
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#define MT6363_RG_LDO_VM18_RC8_OP_MODE_ADDR 0x1CCB
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#define MT6363_RG_LDO_VM18_RC9_OP_MODE_ADDR 0x1CCB
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#define MT6363_RG_LDO_VM18_RC10_OP_MODE_ADDR 0x1CCB
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#define MT6363_RG_LDO_VM18_RC11_OP_MODE_ADDR 0x1CCB
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#define MT6363_RG_LDO_VM18_RC12_OP_MODE_ADDR 0x1CCB
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#define MT6363_RG_LDO_VM18_RC13_OP_MODE_ADDR 0x1CCB
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#define MT6363_RG_LDO_VM18_HW0_OP_MODE_ADDR 0x1CCC
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#define MT6363_RG_LDO_VM18_HW1_OP_MODE_ADDR 0x1CCC
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#define MT6363_RG_LDO_VM18_HW2_OP_MODE_ADDR 0x1CCC
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#define MT6363_RG_LDO_VM18_HW3_OP_MODE_ADDR 0x1CCC
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#define MT6363_RG_LDO_VM18_HW4_OP_MODE_ADDR 0x1CCC
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#define MT6363_RG_LDO_VM18_HW5_OP_MODE_ADDR 0x1CCC
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#define MT6363_RG_LDO_VM18_HW6_OP_MODE_ADDR 0x1CCC
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#define MT6363_RG_LDO_VCN13_ONLV_EN_ADDR 0x1D08
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#define MT6363_RG_LDO_VCN13_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VCN13_VOSEL_SLEEP_ADDR 0x1D0D
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#define MT6363_RG_LDO_VCN13_RC0_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC1_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC2_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC3_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC4_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC5_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC6_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC7_OP_EN_ADDR 0x1D14
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#define MT6363_RG_LDO_VCN13_RC8_OP_EN_ADDR 0x1D15
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#define MT6363_RG_LDO_VCN13_RC9_OP_EN_ADDR 0x1D15
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#define MT6363_RG_LDO_VCN13_RC10_OP_EN_ADDR 0x1D15
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#define MT6363_RG_LDO_VCN13_RC11_OP_EN_ADDR 0x1D15
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#define MT6363_RG_LDO_VCN13_RC12_OP_EN_ADDR 0x1D15
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#define MT6363_RG_LDO_VCN13_RC13_OP_EN_ADDR 0x1D15
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#define MT6363_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1D16
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#define MT6363_RG_LDO_VCN13_HW1_OP_EN_ADDR 0x1D16
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#define MT6363_RG_LDO_VCN13_HW2_OP_EN_ADDR 0x1D16
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#define MT6363_RG_LDO_VCN13_HW3_OP_EN_ADDR 0x1D16
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#define MT6363_RG_LDO_VCN13_HW4_OP_EN_ADDR 0x1D16
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#define MT6363_RG_LDO_VCN13_HW5_OP_EN_ADDR 0x1D16
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|
#define MT6363_RG_LDO_VCN13_HW6_OP_EN_ADDR 0x1D16
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|
#define MT6363_RG_LDO_VCN13_SW_OP_EN_ADDR 0x1D16
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#define MT6363_RG_LDO_VCN13_RC0_OP_CFG_ADDR 0x1D17
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#define MT6363_RG_LDO_VCN13_RC1_OP_CFG_ADDR 0x1D17
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#define MT6363_RG_LDO_VCN13_RC2_OP_CFG_ADDR 0x1D17
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#define MT6363_RG_LDO_VCN13_RC3_OP_CFG_ADDR 0x1D17
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#define MT6363_RG_LDO_VCN13_RC4_OP_CFG_ADDR 0x1D17
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#define MT6363_RG_LDO_VCN13_RC5_OP_CFG_ADDR 0x1D17
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#define MT6363_RG_LDO_VCN13_RC6_OP_CFG_ADDR 0x1D17
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|
#define MT6363_RG_LDO_VCN13_RC7_OP_CFG_ADDR 0x1D17
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|
#define MT6363_RG_LDO_VCN13_RC8_OP_CFG_ADDR 0x1D18
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|
#define MT6363_RG_LDO_VCN13_RC9_OP_CFG_ADDR 0x1D18
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|
#define MT6363_RG_LDO_VCN13_RC10_OP_CFG_ADDR 0x1D18
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|
#define MT6363_RG_LDO_VCN13_RC11_OP_CFG_ADDR 0x1D18
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|
#define MT6363_RG_LDO_VCN13_RC12_OP_CFG_ADDR 0x1D18
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|
#define MT6363_RG_LDO_VCN13_RC13_OP_CFG_ADDR 0x1D18
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|
#define MT6363_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1D19
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|
#define MT6363_RG_LDO_VCN13_HW1_OP_CFG_ADDR 0x1D19
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|
#define MT6363_RG_LDO_VCN13_HW2_OP_CFG_ADDR 0x1D19
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|
#define MT6363_RG_LDO_VCN13_HW3_OP_CFG_ADDR 0x1D19
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|
#define MT6363_RG_LDO_VCN13_HW4_OP_CFG_ADDR 0x1D19
|
|
#define MT6363_RG_LDO_VCN13_HW5_OP_CFG_ADDR 0x1D19
|
|
#define MT6363_RG_LDO_VCN13_HW6_OP_CFG_ADDR 0x1D19
|
|
#define MT6363_RG_LDO_VCN13_SW_OP_CFG_ADDR 0x1D19
|
|
#define MT6363_RG_LDO_VCN13_RC0_OP_MODE_ADDR 0x1D1A
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|
#define MT6363_RG_LDO_VCN13_RC1_OP_MODE_ADDR 0x1D1A
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|
#define MT6363_RG_LDO_VCN13_RC2_OP_MODE_ADDR 0x1D1A
|
|
#define MT6363_RG_LDO_VCN13_RC3_OP_MODE_ADDR 0x1D1A
|
|
#define MT6363_RG_LDO_VCN13_RC4_OP_MODE_ADDR 0x1D1A
|
|
#define MT6363_RG_LDO_VCN13_RC5_OP_MODE_ADDR 0x1D1A
|
|
#define MT6363_RG_LDO_VCN13_RC6_OP_MODE_ADDR 0x1D1A
|
|
#define MT6363_RG_LDO_VCN13_RC7_OP_MODE_ADDR 0x1D1A
|
|
#define MT6363_RG_LDO_VCN13_RC8_OP_MODE_ADDR 0x1D1B
|
|
#define MT6363_RG_LDO_VCN13_RC9_OP_MODE_ADDR 0x1D1B
|
|
#define MT6363_RG_LDO_VCN13_RC10_OP_MODE_ADDR 0x1D1B
|
|
#define MT6363_RG_LDO_VCN13_RC11_OP_MODE_ADDR 0x1D1B
|
|
#define MT6363_RG_LDO_VCN13_RC12_OP_MODE_ADDR 0x1D1B
|
|
#define MT6363_RG_LDO_VCN13_RC13_OP_MODE_ADDR 0x1D1B
|
|
#define MT6363_RG_LDO_VCN13_HW0_OP_MODE_ADDR 0x1D1C
|
|
#define MT6363_RG_LDO_VCN13_HW1_OP_MODE_ADDR 0x1D1C
|
|
#define MT6363_RG_LDO_VCN13_HW2_OP_MODE_ADDR 0x1D1C
|
|
#define MT6363_RG_LDO_VCN13_HW3_OP_MODE_ADDR 0x1D1C
|
|
#define MT6363_RG_LDO_VCN13_HW4_OP_MODE_ADDR 0x1D1C
|
|
#define MT6363_RG_LDO_VCN13_HW5_OP_MODE_ADDR 0x1D1C
|
|
#define MT6363_RG_LDO_VCN13_HW6_OP_MODE_ADDR 0x1D1C
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_ONLV_EN_ADDR 0x1D1E
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_ONLV_EN_SHIFT 3
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_SLEEP_ADDR 0x1D23
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_EN_ADDR 0x1D2A
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_EN_ADDR 0x1D2B
|
|
#define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_EN_ADDR 0x1D2B
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_EN_ADDR 0x1D2B
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_EN_ADDR 0x1D2B
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_EN_ADDR 0x1D2B
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_EN_ADDR 0x1D2B
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_SW_OP_EN_ADDR 0x1D2C
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_CFG_ADDR 0x1D2D
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_CFG_ADDR 0x1D2E
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_CFG_ADDR 0x1D2E
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_CFG_ADDR 0x1D2E
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_CFG_ADDR 0x1D2E
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_CFG_ADDR 0x1D2E
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_CFG_ADDR 0x1D2E
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_SW_OP_CFG_ADDR 0x1D2F
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_MODE_ADDR 0x1D30
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_MODE_ADDR 0x1D31
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_MODE_ADDR 0x1D31
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_MODE_ADDR 0x1D31
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_MODE_ADDR 0x1D31
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_MODE_ADDR 0x1D31
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#define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_MODE_ADDR 0x1D31
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_MODE_ADDR 0x1D32
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_MODE_ADDR 0x1D32
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_MODE_ADDR 0x1D32
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_MODE_ADDR 0x1D32
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_MODE_ADDR 0x1D32
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_MODE_ADDR 0x1D32
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#define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_MODE_ADDR 0x1D32
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#define MT6363_RG_LDO_VSRAM_MDFE_ONLV_EN_ADDR 0x1D88
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#define MT6363_RG_LDO_VSRAM_MDFE_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_SLEEP_ADDR 0x1D8D
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#define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_EN_ADDR 0x1D94
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#define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_EN_ADDR 0x1D95
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#define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_EN_ADDR 0x1D95
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#define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_EN_ADDR 0x1D95
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#define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_EN_ADDR 0x1D95
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#define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_EN_ADDR 0x1D95
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#define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_EN_ADDR 0x1D95
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#define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_SW_OP_EN_ADDR 0x1D96
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#define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_CFG_ADDR 0x1D97
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#define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_CFG_ADDR 0x1D98
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#define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_CFG_ADDR 0x1D98
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#define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_CFG_ADDR 0x1D98
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#define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_CFG_ADDR 0x1D98
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#define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_CFG_ADDR 0x1D98
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#define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_CFG_ADDR 0x1D98
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#define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_SW_OP_CFG_ADDR 0x1D99
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#define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_MODE_ADDR 0x1D9A
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#define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_MODE_ADDR 0x1D9B
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#define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_MODE_ADDR 0x1D9B
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#define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_MODE_ADDR 0x1D9B
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#define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_MODE_ADDR 0x1D9B
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#define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_MODE_ADDR 0x1D9B
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#define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_MODE_ADDR 0x1D9B
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#define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_MODE_ADDR 0x1D9C
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#define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_MODE_ADDR 0x1D9C
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#define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_MODE_ADDR 0x1D9C
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#define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_MODE_ADDR 0x1D9C
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#define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_MODE_ADDR 0x1D9C
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#define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_MODE_ADDR 0x1D9C
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#define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_MODE_ADDR 0x1D9C
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#define MT6363_RG_LDO_VSRAM_MODEM_ONLV_EN_ADDR 0x1DA3
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#define MT6363_RG_LDO_VSRAM_MODEM_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_SLEEP_ADDR 0x1DA8
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#define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_EN_ADDR 0x1DAF
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#define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_EN_ADDR 0x1DB0
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#define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_EN_ADDR 0x1DB0
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#define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_EN_ADDR 0x1DB0
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#define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_EN_ADDR 0x1DB0
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#define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_EN_ADDR 0x1DB0
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#define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_EN_ADDR 0x1DB0
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#define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_SW_OP_EN_ADDR 0x1DB1
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#define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_CFG_ADDR 0x1DB2
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#define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_CFG_ADDR 0x1DB3
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#define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_CFG_ADDR 0x1DB3
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#define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_CFG_ADDR 0x1DB3
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#define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_CFG_ADDR 0x1DB3
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#define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_CFG_ADDR 0x1DB3
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#define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_CFG_ADDR 0x1DB3
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#define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_SW_OP_CFG_ADDR 0x1DB4
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#define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_MODE_ADDR 0x1DB5
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#define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_MODE_ADDR 0x1DB6
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#define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_MODE_ADDR 0x1DB6
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#define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_MODE_ADDR 0x1DB6
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#define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_MODE_ADDR 0x1DB6
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#define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_MODE_ADDR 0x1DB6
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#define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_MODE_ADDR 0x1DB6
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#define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_MODE_ADDR 0x1DB7
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#define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_MODE_ADDR 0x1DB7
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#define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_MODE_ADDR 0x1DB7
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#define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_MODE_ADDR 0x1DB7
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#define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_MODE_ADDR 0x1DB7
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#define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_MODE_ADDR 0x1DB7
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#define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_MODE_ADDR 0x1DB7
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#define MT6363_RG_LDO_VSRAM_CPUB_ONLV_EN_ADDR 0x1E08
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#define MT6363_RG_LDO_VSRAM_CPUB_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_SLEEP_ADDR 0x1E0D
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#define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_EN_ADDR 0x1E14
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#define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_EN_ADDR 0x1E15
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#define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_EN_ADDR 0x1E15
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#define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_EN_ADDR 0x1E15
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#define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_EN_ADDR 0x1E15
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#define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_EN_ADDR 0x1E15
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#define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_EN_ADDR 0x1E15
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#define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_SW_OP_EN_ADDR 0x1E16
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#define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_CFG_ADDR 0x1E17
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#define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_CFG_ADDR 0x1E18
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#define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_CFG_ADDR 0x1E18
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#define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_CFG_ADDR 0x1E18
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#define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_CFG_ADDR 0x1E18
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#define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_CFG_ADDR 0x1E18
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#define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_CFG_ADDR 0x1E18
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#define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_SW_OP_CFG_ADDR 0x1E19
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#define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_MODE_ADDR 0x1E1A
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#define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_MODE_ADDR 0x1E1B
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#define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_MODE_ADDR 0x1E1B
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#define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_MODE_ADDR 0x1E1B
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#define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_MODE_ADDR 0x1E1B
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#define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_MODE_ADDR 0x1E1B
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#define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_MODE_ADDR 0x1E1B
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#define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_MODE_ADDR 0x1E1C
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#define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_MODE_ADDR 0x1E1C
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#define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_MODE_ADDR 0x1E1C
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#define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_MODE_ADDR 0x1E1C
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#define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_MODE_ADDR 0x1E1C
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#define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_MODE_ADDR 0x1E1C
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#define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_MODE_ADDR 0x1E1C
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#define MT6363_RG_LDO_VSRAM_CPUM_ONLV_EN_ADDR 0x1E1E
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#define MT6363_RG_LDO_VSRAM_CPUM_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_SLEEP_ADDR 0x1E23
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#define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_EN_ADDR 0x1E2A
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#define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_EN_ADDR 0x1E2B
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#define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_EN_ADDR 0x1E2B
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#define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_EN_ADDR 0x1E2B
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#define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_EN_ADDR 0x1E2B
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#define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_EN_ADDR 0x1E2B
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#define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_EN_ADDR 0x1E2B
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#define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_SW_OP_EN_ADDR 0x1E2C
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#define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_CFG_ADDR 0x1E2D
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#define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_CFG_ADDR 0x1E2E
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#define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_CFG_ADDR 0x1E2E
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#define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_CFG_ADDR 0x1E2E
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#define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_CFG_ADDR 0x1E2E
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#define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_CFG_ADDR 0x1E2E
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#define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_CFG_ADDR 0x1E2E
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#define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_SW_OP_CFG_ADDR 0x1E2F
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#define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_MODE_ADDR 0x1E30
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#define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_MODE_ADDR 0x1E31
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#define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_MODE_ADDR 0x1E31
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#define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_MODE_ADDR 0x1E31
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#define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_MODE_ADDR 0x1E31
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#define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_MODE_ADDR 0x1E31
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#define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_MODE_ADDR 0x1E31
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#define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_MODE_ADDR 0x1E32
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#define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_MODE_ADDR 0x1E32
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#define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_MODE_ADDR 0x1E32
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#define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_MODE_ADDR 0x1E32
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#define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_MODE_ADDR 0x1E32
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#define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_MODE_ADDR 0x1E32
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#define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_MODE_ADDR 0x1E32
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#define MT6363_RG_LDO_VSRAM_CPUL_ONLV_EN_ADDR 0x1E88
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#define MT6363_RG_LDO_VSRAM_CPUL_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_SLEEP_ADDR 0x1E8D
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#define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_EN_ADDR 0x1E94
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#define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_EN_ADDR 0x1E95
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#define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_EN_ADDR 0x1E95
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#define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_EN_ADDR 0x1E95
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#define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_EN_ADDR 0x1E95
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#define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_EN_ADDR 0x1E95
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#define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_EN_ADDR 0x1E95
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#define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_SW_OP_EN_ADDR 0x1E96
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#define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_CFG_ADDR 0x1E97
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#define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_CFG_ADDR 0x1E98
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#define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_CFG_ADDR 0x1E98
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#define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_CFG_ADDR 0x1E98
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#define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_CFG_ADDR 0x1E98
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#define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_CFG_ADDR 0x1E98
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#define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_CFG_ADDR 0x1E98
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#define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_SW_OP_CFG_ADDR 0x1E99
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#define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_MODE_ADDR 0x1E9A
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#define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_MODE_ADDR 0x1E9B
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#define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_MODE_ADDR 0x1E9B
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#define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_MODE_ADDR 0x1E9B
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#define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_MODE_ADDR 0x1E9B
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#define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_MODE_ADDR 0x1E9B
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#define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_MODE_ADDR 0x1E9B
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#define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_MODE_ADDR 0x1E9C
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#define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_MODE_ADDR 0x1E9C
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#define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_MODE_ADDR 0x1E9C
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#define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_MODE_ADDR 0x1E9C
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#define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_MODE_ADDR 0x1E9C
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#define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_MODE_ADDR 0x1E9C
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#define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_MODE_ADDR 0x1E9C
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#define MT6363_RG_LDO_VSRAM_APU_ONLV_EN_ADDR 0x1E9E
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#define MT6363_RG_LDO_VSRAM_APU_ONLV_EN_SHIFT 3
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#define MT6363_RG_LDO_VSRAM_APU_VOSEL_SLEEP_ADDR 0x1EA3
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#define MT6363_RG_LDO_VSRAM_APU_RC0_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC1_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC2_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC3_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC4_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC5_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC6_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC7_OP_EN_ADDR 0x1EAA
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#define MT6363_RG_LDO_VSRAM_APU_RC8_OP_EN_ADDR 0x1EAB
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#define MT6363_RG_LDO_VSRAM_APU_RC9_OP_EN_ADDR 0x1EAB
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#define MT6363_RG_LDO_VSRAM_APU_RC10_OP_EN_ADDR 0x1EAB
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#define MT6363_RG_LDO_VSRAM_APU_RC11_OP_EN_ADDR 0x1EAB
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#define MT6363_RG_LDO_VSRAM_APU_RC12_OP_EN_ADDR 0x1EAB
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#define MT6363_RG_LDO_VSRAM_APU_RC13_OP_EN_ADDR 0x1EAB
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#define MT6363_RG_LDO_VSRAM_APU_HW0_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_HW1_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_HW2_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_HW3_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_HW4_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_HW5_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_HW6_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_SW_OP_EN_ADDR 0x1EAC
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#define MT6363_RG_LDO_VSRAM_APU_RC0_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC1_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC2_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC3_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC4_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC5_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC6_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC7_OP_CFG_ADDR 0x1EAD
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#define MT6363_RG_LDO_VSRAM_APU_RC8_OP_CFG_ADDR 0x1EAE
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#define MT6363_RG_LDO_VSRAM_APU_RC9_OP_CFG_ADDR 0x1EAE
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#define MT6363_RG_LDO_VSRAM_APU_RC10_OP_CFG_ADDR 0x1EAE
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#define MT6363_RG_LDO_VSRAM_APU_RC11_OP_CFG_ADDR 0x1EAE
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#define MT6363_RG_LDO_VSRAM_APU_RC12_OP_CFG_ADDR 0x1EAE
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#define MT6363_RG_LDO_VSRAM_APU_RC13_OP_CFG_ADDR 0x1EAE
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#define MT6363_RG_LDO_VSRAM_APU_HW0_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_HW1_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_HW2_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_HW3_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_HW4_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_HW5_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_HW6_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_SW_OP_CFG_ADDR 0x1EAF
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#define MT6363_RG_LDO_VSRAM_APU_RC0_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC1_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC2_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC3_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC4_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC5_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC6_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC7_OP_MODE_ADDR 0x1EB0
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#define MT6363_RG_LDO_VSRAM_APU_RC8_OP_MODE_ADDR 0x1EB1
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#define MT6363_RG_LDO_VSRAM_APU_RC9_OP_MODE_ADDR 0x1EB1
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#define MT6363_RG_LDO_VSRAM_APU_RC10_OP_MODE_ADDR 0x1EB1
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#define MT6363_RG_LDO_VSRAM_APU_RC11_OP_MODE_ADDR 0x1EB1
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#define MT6363_RG_LDO_VSRAM_APU_RC12_OP_MODE_ADDR 0x1EB1
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#define MT6363_RG_LDO_VSRAM_APU_RC13_OP_MODE_ADDR 0x1EB1
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#define MT6363_RG_LDO_VSRAM_APU_HW0_OP_MODE_ADDR 0x1EB2
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#define MT6363_RG_LDO_VSRAM_APU_HW1_OP_MODE_ADDR 0x1EB2
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#define MT6363_RG_LDO_VSRAM_APU_HW2_OP_MODE_ADDR 0x1EB2
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#define MT6363_RG_LDO_VSRAM_APU_HW3_OP_MODE_ADDR 0x1EB2
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#define MT6363_RG_LDO_VSRAM_APU_HW4_OP_MODE_ADDR 0x1EB2
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#define MT6363_RG_LDO_VSRAM_APU_HW5_OP_MODE_ADDR 0x1EB2
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#define MT6363_RG_LDO_VSRAM_APU_HW6_OP_MODE_ADDR 0x1EB2
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT0_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT1_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT2_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT3_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT4_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT5_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT6_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT7_ADDR 0x189A
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#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT0_ADDR 0x189D
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#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT1_ADDR 0x189D
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#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT2_ADDR 0x189D
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#define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT3_ADDR 0x189D
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT0_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT1_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT2_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT3_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT4_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT5_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT6_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT7_ADDR 0x149A
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#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT0_ADDR 0x149D
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#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT1_ADDR 0x149D
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#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT2_ADDR 0x149D
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#define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT3_ADDR 0x149D
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT0_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT1_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT2_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT3_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT4_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT5_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT6_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT7_ADDR 0x191A
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#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT0_ADDR 0x191D
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#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT1_ADDR 0x191D
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#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT2_ADDR 0x191D
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#define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT3_ADDR 0x191D
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#endif /* MT6363_LOWPOWER_REG_H */
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