Manish Pandey d435238dc3 fix(bl31): harden check in delegate_async_ea ... Following hardening done around ESR_EL3 register usage - Panic if exception is anyting other than SError - AET bit is only valid if DFSC is 0x11, move DFSC check before AET. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib15159920f6cad964332fd40f88943aee2bc73b4		2022-11-07 21:04:42 +00:00
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aarch64	fix(bl31): harden check in delegate_async_ea	2022-11-07 21:04:42 +00:00
bl31.ld.S	Merge "refactor(bl31): introduce vendor extend rodata section" into integration	2022-08-16 02:12:01 +02:00
bl31.mk	feat(drtm): add remediation driver support in DRTM	2022-10-05 15:25:28 +01:00
bl31_context_mgmt.c	feat(rme): add context management changes for FEAT_RME	2021-10-05 18:41:35 +02:00
bl31_main.c	refactor(context mgmt): add cm_prepare_el3_exit_ns function	2022-04-12 17:42:11 +02:00
ehf.c	fix(bl31): allow use of EHF with S-EL2 SPMC	2022-08-30 08:29:25 -07:00
interrupt_mgmt.c	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00