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https://github.com/ARM-software/arm-trusted-firmware.git
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d3996c590d
On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock rate is managed by SCFW(system controller firmware) and can ONLY be changed from secure world, so SIP runtime service is needed for setting CPU's clock rate, this patch adds cpu-freq SIP runtime service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
78 lines
1.5 KiB
C
78 lines
1.5 KiB
C
/*
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* Copyright 2019 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <std_svc.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <imx_sip_svc.h>
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#include <sci/sci.h>
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#ifdef PLAT_IMX8QM
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const static int ap_cluster_index[PLATFORM_CLUSTER_COUNT] = {
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SC_R_A53, SC_R_A72,
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};
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#endif
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static int imx_srtc_set_time(uint32_t year_mon,
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unsigned long day_hour,
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unsigned long min_sec)
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{
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return sc_timer_set_rtc_time(ipc_handle,
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year_mon >> 16, year_mon & 0xffff,
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day_hour >> 16, day_hour & 0xffff,
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min_sec >> 16, min_sec & 0xffff);
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}
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int imx_srtc_handler(uint32_t smc_fid,
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void *handle,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4)
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{
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int ret;
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switch (x1) {
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case IMX_SIP_SRTC_SET_TIME:
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ret = imx_srtc_set_time(x2, x3, x4);
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break;
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default:
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ret = SMC_UNK;
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}
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SMC_RET1(handle, ret);
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}
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static void imx_cpufreq_set_target(uint32_t cluster_id, unsigned long freq)
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{
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sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq;
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#ifdef PLAT_IMX8QM
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sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate);
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#endif
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#ifdef PLAT_IMX8QX
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sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate);
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#endif
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}
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int imx_cpufreq_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3)
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{
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switch (x1) {
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case IMX_SIP_SET_CPUFREQ:
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imx_cpufreq_set_target(x2, x3);
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break;
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default:
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return SMC_UNK;
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}
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return 0;
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}
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