mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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d31ffcf0f7
Add system reset support for i.MX8QM, when Linux kernel issues "reboot" command, TF-A will send command to inform system controller to reset whole board according to board design, tested on i.MX8QM MEK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
116 lines
3 KiB
C
116 lines
3 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <cci.h>
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#include <debug.h>
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#include <gicv3.h>
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#include <mmio.h>
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#include <plat_imx8.h>
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#include <psci.h>
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#include <sci/sci.h>
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#include <stdbool.h>
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const static int ap_core_index[PLATFORM_CORE_COUNT] = {
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SC_R_A53_0, SC_R_A53_1, SC_R_A53_2,
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SC_R_A53_3, SC_R_A72_0, SC_R_A72_1,
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};
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/* need to enable USE_COHERENT_MEM to avoid coherence issue */
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#if USE_COHERENT_MEM
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static unsigned int a53_cpu_on_number __section("tzfw_coherent_mem");
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static unsigned int a72_cpu_on_number __section("tzfw_coherent_mem");
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#endif
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int imx_pwr_domain_on(u_register_t mpidr)
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{
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int ret = PSCI_E_SUCCESS;
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unsigned int cluster_id, cpu_id;
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cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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tf_printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id);
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if (cluster_id == 0) {
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if (a53_cpu_on_number == 0)
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON);
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if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
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ERROR("cluster0 core %d power on failed!\n", cpu_id);
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ret = PSCI_E_INTERN_FAIL;
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}
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if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id],
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true, BL31_BASE) != SC_ERR_NONE) {
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ERROR("boot cluster0 core %d failed!\n", cpu_id);
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ret = PSCI_E_INTERN_FAIL;
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}
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} else {
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if (a72_cpu_on_number == 0)
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON);
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if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id + 4],
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SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
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ERROR(" cluster1 core %d power on failed!\n", cpu_id);
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ret = PSCI_E_INTERN_FAIL;
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}
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if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id + 4],
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true, BL31_BASE) != SC_ERR_NONE) {
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ERROR("boot cluster1 core %d failed!\n", cpu_id);
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ret = PSCI_E_INTERN_FAIL;
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}
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}
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return ret;
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}
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void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint64_t mpidr = read_mpidr_el1();
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unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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if (cluster_id == 0 && a53_cpu_on_number++ == 0)
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cci_enable_snoop_dvm_reqs(0);
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if (cluster_id == 1 && a72_cpu_on_number++ == 0)
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cci_enable_snoop_dvm_reqs(1);
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plat_gic_pcpu_init();
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plat_gic_cpuif_enable();
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}
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int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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return PSCI_E_SUCCESS;
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}
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static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_on = imx_pwr_domain_on,
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.pwr_domain_on_finish = imx_pwr_domain_on_finish,
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.validate_ns_entrypoint = imx_validate_ns_entrypoint,
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.system_off = imx_system_off,
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.system_reset = imx_system_reset,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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uint64_t mpidr = read_mpidr_el1();
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unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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imx_mailbox_init(sec_entrypoint);
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*psci_ops = &imx_plat_psci_ops;
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if (cluster_id == 0)
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a53_cpu_on_number++;
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else
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a72_cpu_on_number++;
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return 0;
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}
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