mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
d2e44e7d71
The gic and trbe0 are listed as active high, but the spec says they are triggered on active low. Correct according to the spec. While we're at it, convert all interrupts to use the macros so hopefully no such confusion happens again. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I2fc01cf0a34b031b95219b9656b613a19a2e9b2a
613 lines
13 KiB
Text
613 lines
13 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "arm,tc";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &ap_ns_uart;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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/*
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* The timings below are just to demonstrate working cpuidle.
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* These values may be inaccurate.
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*/
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2000>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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local-timer-stop;
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entry-latency-us = <400>;
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exit-latency-us = <1200>;
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min-residency-us = <2500>;
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};
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};
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amus {
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amu: amu-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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mpmm_gear0: counter@0 {
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reg = <0>;
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enable-at-el3;
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};
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mpmm_gear1: counter@1 {
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reg = <1>;
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enable-at-el3;
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};
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mpmm_gear2: counter@2 {
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reg = <2>;
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enable-at-el3;
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};
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};
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};
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU1:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x100>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU2:cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x200>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU3:cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x300>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU4:cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x400>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <912>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU5:cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x500>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <912>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU6:cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x600>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <912>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU7:cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x700>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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amu = <&amu>;
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supports-mpmm;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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linux,cma-default;
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};
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optee@0xf8e00000 {
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compatible = "restricted-dma-pool";
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reg = <0x00000000 0xf8e00000 0 0x00200000>;
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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sram: sram@6000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x06000000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x06000000 0x8000>;
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cpu_scp_scmi_mem: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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};
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mbox_db_rx: mhu@45010000 {
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compatible = "arm,mhuv2-rx","arm,primecell";
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reg = <0x0 0x45010000 0x0 0x1000>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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#mbox-cells = <2>;
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interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mhu_rx";
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mhu-protocol = "doorbell";
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arm,mhuv2-protocols = <0 1>;
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};
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mbox_db_tx: mhu@45000000 {
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compatible = "arm,mhuv2-tx","arm,primecell";
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reg = <0x0 0x45000000 0x0 0x1000>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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#mbox-cells = <2>;
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interrupt-names = "mhu_tx";
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mhu-protocol = "doorbell";
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arm,mhuv2-protocols = <0 1>;
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};
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cmn-pmu {
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compatible = "arm,ci-700";
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reg = <0x0 0x50000000 0x0 0x10000000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
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};
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
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shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-600", "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x30080000 0 0x200000>; /* GICR */
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interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc_refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_refclk60mhz: refclk60mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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clock-output-names = "iofpga_clk";
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};
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soc_uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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ap_ns_uart: uart@2A400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2A400000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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status = "okay";
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};
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rtc0: rtc@1C170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x0 0x1C170000 0x0 0x1000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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wakeup-source;
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};
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vencoder {
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compatible = "drm,virtual-encoder";
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port {
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vencoder_in: endpoint {
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remote-endpoint = <&dp_pl0_out0>;
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};
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};
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display-timings {
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panel-timing {
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clock-frequency = <25175000>;
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hactive = <640>;
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vactive = <480>;
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hfront-porch = <16>;
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hback-porch = <48>;
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hsync-len = <96>;
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vfront-porch = <10>;
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vback-porch = <33>;
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vsync-len = <2>;
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};
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};
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};
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hdlcd: hdlcd@7ff60000 {
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compatible = "arm,hdlcd";
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reg = <0x0 0x7ff60000 0x0 0x1000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fake_hdlcd_clk>;
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clock-names = "pxlclk";
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status = "disabled";
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port {
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hdlcd_out: endpoint {
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remote-endpoint = <&vencoder_in>;
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};
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};
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};
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fake_hdlcd_clk: fake-hdlcd-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25175000>;
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clock-output-names = "pxlclk";
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};
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ethernet@18000000 {
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compatible = "smsc,lan91c111";
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reg = <0x0 0x18000000 0x0 0x10000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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};
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kmi@1c060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c060000 0x0 0x1000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c070000 0x0 0x1000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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bp_clock24mhz: clock24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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virtio_block@1c130000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c130000 0x0 0x200>;
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/* spec lists this wrong */
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysreg: sysreg@1c010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x0 0x001c010000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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fixed_3v3: v2m-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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mmci@1c050000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x0 0x001c050000 0x0 0x1000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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cd-gpios = <&sysreg 0 0>;
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wp-gpios = <&sysreg 1 0>;
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bus-width = <8>;
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max-frequency = <12000000>;
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vmmc-supply = <&fixed_3v3>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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gpu_clk: gpu_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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};
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gpu_core_clk: gpu_core_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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};
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gpu: gpu@2d000000 {
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compatible = "arm,mali-midgard";
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reg = <0x0 0x2d000000 0x0 0x200000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "JOB", "MMU", "GPU";
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clocks = <&gpu_core_clk>;
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clock-names = "shadercores";
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power-domains = <&scmi_devpd 9>;
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scmi-perf-domain = <3>;
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iommus = <&smmu_700 0x200>;
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};
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power_model@simple {
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/*
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* Numbers used are irrelevant to Titan,
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* it helps suppressing the kernel warnings.
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*/
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compatible = "arm,mali-simple-power-model";
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static-coefficient = <2427750>;
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dynamic-coefficient = <4687>;
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ts = <20000 2000 (-20) 2>;
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thermal-zone = "";
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};
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smmu_700: smmu_700@3f000000 {
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#iommu-cells = <1>;
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compatible = "arm,smmu-v3";
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reg = <0x0 0x3f000000 0x0 0x5000000>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "cmdq-sync", "gerror";
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dma-coherent;
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};
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dp0: display@2cc00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "arm,mali-d71";
|
|
reg = <0 0x2cc00000 0 0x20000>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "DPU";
|
|
clocks = <&scmi_clk 0>;
|
|
clock-names = "aclk";
|
|
iommus = <&smmu_700 0x100>;
|
|
power-domains = <&scmi_devpd 10>;
|
|
pl0: pipeline@0 {
|
|
reg = <0>;
|
|
clocks = <&scmi_clk 1>;
|
|
clock-names = "pxclk";
|
|
pl_id = <0>;
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
dp_pl0_out0: endpoint {
|
|
remote-endpoint = <&vencoder_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pl1: pipeline@1 {
|
|
reg = <1>;
|
|
clocks = <&scmi_clk 2>;
|
|
clock-names = "pxclk";
|
|
pl_id = <1>;
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* L3 cache in the DSU is the Memory System Component (MSC)
|
|
* The MPAM registers are accessed through utility bus in the DSU
|
|
*/
|
|
msc0 {
|
|
compatible = "arm,mpam-msc";
|
|
reg = <0x1 0x00010000 0x0 0x2000>;
|
|
};
|
|
|
|
ete0 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
ete1 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
ete2 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU2>;
|
|
};
|
|
|
|
ete3 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU3>;
|
|
};
|
|
|
|
ete4 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU4>;
|
|
};
|
|
|
|
ete5 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU5>;
|
|
};
|
|
|
|
ete6 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU6>;
|
|
};
|
|
|
|
ete7 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU7>;
|
|
};
|
|
|
|
trbe0 {
|
|
compatible = "arm,trace-buffer-extension";
|
|
interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|