mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 02:24:18 +00:00
d178637d2b
This patch removes the dash character from the image name, to
follow the image terminology in the Trusted Firmware Wiki page:
https://github.com/ARM-software/arm-trusted-firmware/wiki
Changes apply to output messages, comments and documentation.
non-ARM platform files have been left unmodified.
Change-Id: Ic2a99be4ed929d52afbeb27ac765ceffce46ed76
266 lines
9.8 KiB
ArmAsm
266 lines
9.8 KiB
ArmAsm
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __EL3_COMMON_MACROS_S__
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#define __EL3_COMMON_MACROS_S__
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#include <arch.h>
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#include <asm_macros.S>
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/*
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* Helper macro to initialise EL3 registers we care about.
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*/
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.macro el3_arch_init_common _exception_vectors
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/* ---------------------------------------------------------------------
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* Enable the instruction cache, stack pointer and data access alignment
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* checks
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* ---------------------------------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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#if IMAGE_BL31
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/* ---------------------------------------------------------------------
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* Initialise the per-cpu cache pointer to the CPU.
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* This is done early to enable crash reporting to have access to crash
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* stack. Since crash reporting depends on cpu_data to report the
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* unhandled exception, not doing so can lead to recursive exceptions
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* due to a NULL TPIDR_EL3.
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* ---------------------------------------------------------------------
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*/
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bl init_cpu_data_ptr
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#endif /* IMAGE_BL31 */
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/* ---------------------------------------------------------------------
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* Set the exception vectors.
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* ---------------------------------------------------------------------
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*/
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adr x0, \_exception_vectors
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msr vbar_el3, x0
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isb
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/* ---------------------------------------------------------------------
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* Enable the SError interrupt now that the exception vectors have been
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* setup.
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* ---------------------------------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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*
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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*
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x0, cptr_el3
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bic w0, w0, #TCPAC_BIT
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bic w0, w0, #TTA_BIT
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bic w0, w0, #TFP_BIT
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msr cptr_el3, x0
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.endm
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/* -----------------------------------------------------------------------------
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* This is the super set of actions that need to be performed during a cold boot
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* or a warm boot in EL3. This code is shared by BL1 and BL31.
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*
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* This macro will always perform reset handling, architectural initialisations
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* and stack setup. The rest of the actions are optional because they might not
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* be needed, depending on the context in which this macro is called. This is
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* why this macro is parameterised ; each parameter allows to enable/disable
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* some actions.
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*
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* _set_endian:
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* Whether the macro needs to configure the endianness of data accesses.
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*
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* _warm_boot_mailbox:
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* Whether the macro needs to detect the type of boot (cold/warm). The
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* detection is based on the platform entrypoint address : if it is zero
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* then it is a cold boot, otherwise it is a warm boot. In the latter case,
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* this macro jumps on the platform entrypoint address.
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*
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* _secondary_cold_boot:
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* Whether the macro needs to identify the CPU that is calling it: primary
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* CPU or secondary CPU. The primary CPU will be allowed to carry on with
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* the platform initialisations, while the secondaries will be put in a
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* platform-specific state in the meantime.
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*
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* If the caller knows this macro will only be called by the primary CPU
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* then this parameter can be defined to 0 to skip this step.
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*
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* _init_memory:
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* Whether the macro needs to initialise the memory.
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*
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* _init_c_runtime:
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* Whether the macro needs to initialise the C runtime environment.
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*
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* _exception_vectors:
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* Address of the exception vectors to program in the VBAR_EL3 register.
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* -----------------------------------------------------------------------------
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*/
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.macro el3_entrypoint_common \
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_set_endian, _warm_boot_mailbox, _secondary_cold_boot, \
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_init_memory, _init_c_runtime, _exception_vectors
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.if \_set_endian
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/* -------------------------------------------------------------
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* Set the CPU endianness before doing anything that might
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* involve memory reads or writes.
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* -------------------------------------------------------------
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*/
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mrs x0, sctlr_el3
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bic x0, x0, #SCTLR_EE_BIT
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msr sctlr_el3, x0
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isb
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.endif /* _set_endian */
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.if \_warm_boot_mailbox
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/* -------------------------------------------------------------
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* This code will be executed for both warm and cold resets.
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* Now is the time to distinguish between the two.
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* Query the platform entrypoint address and if it is not zero
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* then it means it is a warm boot so jump to this address.
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* -------------------------------------------------------------
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*/
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bl plat_get_my_entrypoint
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cbz x0, do_cold_boot
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br x0
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do_cold_boot:
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.endif /* _warm_boot_mailbox */
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.if \_secondary_cold_boot
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/* -------------------------------------------------------------
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* It is a cold boot.
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* The primary CPU will set up the platform while the
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* secondaries are placed in a platform-specific state until the
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* primary CPU performs the necessary actions to bring them out
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* of that state and allows entry into the OS.
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* -------------------------------------------------------------
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*/
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bl plat_is_my_cpu_primary
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cbnz w0, do_primary_cold_boot
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/* This is a cold boot on a secondary CPU */
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bl plat_secondary_cold_boot_setup
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/* plat_secondary_cold_boot_setup() is not supposed to return */
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secondary_panic:
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b secondary_panic
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do_primary_cold_boot:
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.endif /* _secondary_cold_boot */
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/* ---------------------------------------------------------------------
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* Perform any processor specific actions upon reset e.g. cache, TLB
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* invalidations etc.
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* ---------------------------------------------------------------------
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*/
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bl reset_handler
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el3_arch_init_common \_exception_vectors
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.if \_init_memory
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bl platform_mem_init
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.endif /* _init_memory */
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/* ---------------------------------------------------------------------
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* Init C runtime environment:
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* - Zero-initialise the NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section (if any).
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* - Relocate the data section from ROM to RAM, if required.
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* ---------------------------------------------------------------------
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*/
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.if \_init_c_runtime
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#if IMAGE_BL31
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/* -------------------------------------------------------------
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* Invalidate the RW memory used by the BL31 image. This
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* includes the data and NOBITS sections. This is done to
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* safeguard against possible corruption of this memory by
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* dirty cache lines in a system cache as a result of use by
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* an earlier boot loader stage.
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* -------------------------------------------------------------
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*/
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adr x0, __RW_START__
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adr x1, __RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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#endif /* IMAGE_BL31 */
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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#endif
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#if IMAGE_BL1
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ldr x0, =__DATA_RAM_START__
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ldr x1, =__DATA_ROM_START__
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ldr x2, =__DATA_SIZE__
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bl memcpy16
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#endif
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.endif /* _init_c_runtime */
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/* ---------------------------------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------------------------------
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*/
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msr spsel, #0
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/* ---------------------------------------------------------------------
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* Allocate a stack whose memory will be marked as Normal-IS-WBWA when
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* the MMU is enabled. There is no risk of reading stale stack memory
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* after enabling the MMU as only the primary CPU is running at the
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* moment.
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* ---------------------------------------------------------------------
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*/
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bl plat_set_my_stack
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.endm
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#endif /* __EL3_COMMON_MACROS_S__ */
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