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d12afc8e73
Some low end platforms using DMC500 memory controller do not have CCI(Cache Coherent Interconnect) interface and only have non-coherent system interface support. Hence this patch makes the system interface count configurable from the platforms. Change-Id: I6d54c90eb72fd18026c6470c1f7fd26c59dc4b9a Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
151 lines
4.6 KiB
C
151 lines
4.6 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __TZC_DMC500_H__
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#define __TZC_DMC500_H__
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#include <tzc_common.h>
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#define SI_STATUS_OFFSET 0x000
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#define SI_STATE_CTRL_OFFSET 0x030
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#define SI_FLUSH_CTRL_OFFSET 0x034
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#define SI_INT_CONTROL_OFFSET 0x048
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#define SI_INT_STATUS_OFFSET 0x004
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#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET 0x008
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#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET 0x00c
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#define SI_FAIL_CONTROL_OFFSET 0x010
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#define SI_FAIL_ID_OFFSET 0x014
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#define SI_INT_CLR_OFFSET 0x04c
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/*
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* DMC-500 has 2 system interfaces each having a similar set of regs
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* to configure each interface.
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*/
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#define SI0_BASE 0x0000
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#define SI1_BASE 0x0200
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/* Bit positions of SIx_SI_STATUS */
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#define SI_EMPTY_SHIFT 0x01
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#define SI_STALL_ACK_SHIFT 0x00
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#define SI_EMPTY_MASK 0x01
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#define SI_STALL_ACK_MASK 0x01
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/* Bit positions of SIx_SI_INT_STATUS */
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#define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18
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#define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16
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#define PMU_REQ_INT_STATUS_SHIFT 2
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#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1
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#define FAILED_ACCESS_INT_STATUS_SHIFT 0
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#define PMU_REQ_INT_OVERFLOW_STATUS_MASK 0x1
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#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK 0x1
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#define PMU_REQ_INT_STATUS_MASK 0x1
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#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK 0x1
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#define FAILED_ACCESS_INT_STATUS_MASK 0x1
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/* Bit positions of SIx_TZ_FAIL_CONTROL */
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#define DIRECTION_SHIFT 24
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#define NON_SECURE_SHIFT 21
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#define PRIVILEGED_SHIFT 20
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#define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3
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#define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2
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#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 0x1
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#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0
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#define DIRECTION_MASK 0x1
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#define NON_SECURE_MASK 0x1
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#define PRIVILEGED_MASK 0x1
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#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK 0x1
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#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK 0x1
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#define FAILED_ACCESS_INT_TZ_FAIL_MASK 1
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#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK 0x1
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/* Bit positions of SIx_FAIL_STATUS */
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#define FAIL_ID_VNET_SHIFT 24
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#define FAIL_ID_ID_SHIFT 0
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#define FAIL_ID_VNET_MASK 0xf
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#define FAIL_ID_ID_MASK 0xffffff
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/* Bit positions of SIx_SI_STATE_CONTRL */
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#define SI_STALL_REQ_GO 0x0
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#define SI_STALL_REQ_STALL 0x1
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/* Bit positions of SIx_SI_FLUSH_CONTROL */
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#define SI_FLUSH_REQ_INACTIVE 0x0
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#define SI_FLUSH_REQ_ACTIVE 0x1
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#define SI_FLUSH_REQ_MASK 0x1
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/* Bit positions of SIx_SI_INT_CONTROL */
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#define PMU_REQ_INT_EN_SHIFT 2
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#define OVERLAP_DETECT_INT_EN_SHIFT 1
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#define FAILED_ACCESS_INT_EN_SHIFT 0
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#define PMU_REQ_INT_EN_MASK 0x1
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#define OVERLAP_DETECT_INT_EN_MASK 0x1
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#define FAILED_ACCESS_INT_EN_MASK 0x1
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#define PMU_REQ_INT_EN 0x1
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#define OVERLAP_DETECT_INT_EN 0x1
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#define FAILED_ACCESS_INT_EN 0x1
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/* Bit positions of SIx_SI_INT_CLR */
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#define PMU_REQ_OFLOW_CLR_SHIFT 18
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#define FAILED_ACCESS_OFLOW_CLR_SHIFT 16
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#define PMU_REQ_INT_CLR_SHIFT 2
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#define FAILED_ACCESS_INT_CLR_SHIFT 0
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#define PMU_REQ_OFLOW_CLR_MASK 0x1
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#define FAILED_ACCESS_OFLOW_CLR_MASK 0x1
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#define PMU_REQ_INT_CLR_MASK 0x1
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#define FAILED_ACCESS_INT_CLR_MASK 0x1
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#define PMU_REQ_OFLOW_CLR 0x1
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#define FAILED_ACCESS_OFLOW_CLR 0x1
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#define PMU_REQ_INT_CLR 0x1
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#define FAILED_ACCESS_INT_CLR 0x1
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/* Macro to get the correct base register for a system interface */
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#define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE)
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#define MAX_SYS_IF_COUNT 2
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#define MAX_REGION_VAL 8
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/* DMC-500 supports striping across a max of 4 DMC instances */
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#define MAX_DMC_COUNT 4
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/* Consist of part_number_1 and part_number_0 */
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#define DMC500_PERIPHERAL_ID 0x0450
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/* Filter enable bits in a TZC */
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#define TZC_DMC500_REGION_ATTR_F_EN_MASK 0x1
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/* Length of registers for configuring each region */
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#define TZC_DMC500_REGION_SIZE 0x018
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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/*
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* Contains the base addresses of all the DMC instances.
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*/
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typedef struct tzc_dmc500_driver_data {
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uintptr_t dmc_base[MAX_DMC_COUNT];
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int dmc_count;
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unsigned int sys_if_count;
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} tzc_dmc500_driver_data_t;
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void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data);
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void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr,
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unsigned int nsaid_permissions);
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void tzc_dmc500_configure_region(int region_no,
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unsigned long long region_base,
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unsigned long long region_top,
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tzc_region_attributes_t sec_attr,
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unsigned int nsaid_permissions);
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void tzc_dmc500_set_action(tzc_action_t action);
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void tzc_dmc500_config_complete(void);
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int tzc_dmc500_verify_complete(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __TZC_DMC500_H__ */
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