mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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79ca7807cc
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
247 lines
7.6 KiB
C
247 lines
7.6 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DDR_RK3368_H
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#define DDR_RK3368_H
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#define DDR_PCTL_SCFG 0x0
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#define DDR_PCTL_SCTL 0x4
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#define DDR_PCTL_STAT 0x8
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#define DDR_PCTL_INTRSTAT 0xc
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#define DDR_PCTL_MCMD 0x40
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#define DDR_PCTL_POWCTL 0x44
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#define DDR_PCTL_POWSTAT 0x48
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#define DDR_PCTL_CMDTSTAT 0x4c
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#define DDR_PCTL_CMDTSTATEN 0x50
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#define DDR_PCTL_MRRCFG0 0x60
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#define DDR_PCTL_MRRSTAT0 0x64
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#define DDR_PCTL_MRRSTAT1 0x68
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#define DDR_PCTL_MCFG1 0x7c
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#define DDR_PCTL_MCFG 0x80
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#define DDR_PCTL_PPCFG 0x84
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#define DDR_PCTL_MSTAT 0x88
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#define DDR_PCTL_LPDDR2ZQCFG 0x8c
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#define DDR_PCTL_DTUPDES 0x94
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#define DDR_PCTL_DTUNA 0x98
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#define DDR_PCTL_DTUNE 0x9c
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#define DDR_PCTL_DTUPRD0 0xa0
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#define DDR_PCTL_DTUPRD1 0xa4
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#define DDR_PCTL_DTUPRD2 0xa8
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#define DDR_PCTL_DTUPRD3 0xac
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#define DDR_PCTL_DTUAWDT 0xb0
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#define DDR_PCTL_TOGCNT1U 0xc0
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#define DDR_PCTL_TINIT 0xc4
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#define DDR_PCTL_TRSTH 0xc8
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#define DDR_PCTL_TOGCNT100N 0xcc
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#define DDR_PCTL_TREFI 0xd0
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#define DDR_PCTL_TMRD 0xd4
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#define DDR_PCTL_TRFC 0xd8
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#define DDR_PCTL_TRP 0xdc
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#define DDR_PCTL_TRTW 0xe0
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#define DDR_PCTL_TAL 0xe4
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#define DDR_PCTL_TCL 0xe8
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#define DDR_PCTL_TCWL 0xec
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#define DDR_PCTL_TRAS 0xf0
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#define DDR_PCTL_TRC 0xf4
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#define DDR_PCTL_TRCD 0xf8
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#define DDR_PCTL_TRRD 0xfc
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#define DDR_PCTL_TRTP 0x100
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#define DDR_PCTL_TWR 0x104
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#define DDR_PCTL_TWTR 0x108
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#define DDR_PCTL_TEXSR 0x10c
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#define DDR_PCTL_TXP 0x110
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#define DDR_PCTL_TXPDLL 0x114
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#define DDR_PCTL_TZQCS 0x118
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#define DDR_PCTL_TZQCSI 0x11c
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#define DDR_PCTL_TDQS 0x120
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#define DDR_PCTL_TCKSRE 0x124
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#define DDR_PCTL_TCKSRX 0x128
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#define DDR_PCTL_TCKE 0x12c
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#define DDR_PCTL_TMOD 0x130
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#define DDR_PCTL_TRSTL 0x134
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#define DDR_PCTL_TZQCL 0x138
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#define DDR_PCTL_TMRR 0x13c
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#define DDR_PCTL_TCKESR 0x140
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#define DDR_PCTL_TDPD 0x144
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#define DDR_PCTL_TREFI_MEM_DDR3 0x148
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#define DDR_PCTL_ECCCFG 0x180
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#define DDR_PCTL_ECCTST 0x184
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#define DDR_PCTL_ECCCLR 0x188
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#define DDR_PCTL_ECCLOG 0x18c
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#define DDR_PCTL_DTUWACTL 0x200
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#define DDR_PCTL_DTURACTL 0x204
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#define DDR_PCTL_DTUCFG 0x208
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#define DDR_PCTL_DTUECTL 0x20c
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#define DDR_PCTL_DTUWD0 0x210
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#define DDR_PCTL_DTUWD1 0x214
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#define DDR_PCTL_DTUWD2 0x218
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#define DDR_PCTL_DTUWD3 0x21c
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#define DDR_PCTL_DTUWDM 0x220
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#define DDR_PCTL_DTURD0 0x224
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#define DDR_PCTL_DTURD1 0x228
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#define DDR_PCTL_DTURD2 0x22c
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#define DDR_PCTL_DTURD3 0x230
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#define DDR_PCTL_DTULFSRWD 0x234
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#define DDR_PCTL_DTULFSRRD 0x238
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#define DDR_PCTL_DTUEAF 0x23c
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#define DDR_PCTL_DFITCTRLDELAY 0x240
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#define DDR_PCTL_DFIODTCFG 0x244
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#define DDR_PCTL_DFIODTCFG1 0x248
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#define DDR_PCTL_DFIODTRANKMAP 0x24c
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#define DDR_PCTL_DFITPHYWRDATA 0x250
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#define DDR_PCTL_DFITPHYWRLAT 0x254
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#define DDR_PCTL_DFITPHYWRDATALAT 0x258
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#define DDR_PCTL_DFITRDDATAEN 0x260
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#define DDR_PCTL_DFITPHYRDLAT 0x264
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#define DDR_PCTL_DFITPHYUPDTYPE0 0x270
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#define DDR_PCTL_DFITPHYUPDTYPE1 0x274
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#define DDR_PCTL_DFITPHYUPDTYPE2 0x278
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#define DDR_PCTL_DFITPHYUPDTYPE3 0x27c
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#define DDR_PCTL_DFITCTRLUPDMIN 0x280
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#define DDR_PCTL_DFITCTRLUPDMAX 0x284
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#define DDR_PCTL_DFITCTRLUPDDLY 0x288
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#define DDR_PCTL_DFIUPDCFG 0x290
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#define DDR_PCTL_DFITREFMSKI 0x294
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#define DDR_PCTL_DFITCTRLUPDI 0x298
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#define DDR_PCTL_DFITRCFG0 0x2ac
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#define DDR_PCTL_DFITRSTAT0 0x2b0
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#define DDR_PCTL_DFITRWRLVLEN 0x2b4
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#define DDR_PCTL_DFITRRDLVLEN 0x2b8
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#define DDR_PCTL_DFITRRDLVLGATEEN 0x2bc
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#define DDR_PCTL_DFISTSTAT0 0x2c0
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#define DDR_PCTL_DFISTCFG0 0x2c4
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#define DDR_PCTL_DFISTCFG1 0x2c8
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#define DDR_PCTL_DFITDRAMCLKEN 0x2d0
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#define DDR_PCTL_DFITDRAMCLKDIS 0x2d4
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#define DDR_PCTL_DFISTCFG2 0x2d8
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#define DDR_PCTL_DFISTPARCLR 0x2dc
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#define DDR_PCTL_DFISTPARLOG 0x2e0
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#define DDR_PCTL_DFILPCFG0 0x2f0
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#define DDR_PCTL_DFITRWRLVLRESP0 0x300
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#define DDR_PCTL_DFITRWRLVLRESP1 0x304
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#define DDR_PCTL_DFITRWRLVLRESP2 0x308
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#define DDR_PCTL_DFITRRDLVLRESP0 0x30c
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#define DDR_PCTL_DFITRRDLVLRESP1 0x310
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#define DDR_PCTL_DFITRRDLVLRESP2 0x314
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#define DDR_PCTL_DFITRWRLVLDELAY0 0x318
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#define DDR_PCTL_DFITRWRLVLDELAY1 0x31c
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#define DDR_PCTL_DFITRWRLVLDELAY2 0x320
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#define DDR_PCTL_DFITRRDLVLDELAY0 0x324
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#define DDR_PCTL_DFITRRDLVLDELAY1 0x328
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#define DDR_PCTL_DFITRRDLVLDELAY2 0x32c
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#define DDR_PCTL_DFITRRDLVLGATEDELAY0 0x330
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#define DDR_PCTL_DFITRRDLVLGATEDELAY1 0x334
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#define DDR_PCTL_DFITRRDLVLGATEDELAY2 0x338
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#define DDR_PCTL_DFITRCMD 0x33c
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#define DDR_PCTL_IPVR 0x3f8
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#define DDR_PCTL_IPTR 0x3fc
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/* DDR PHY REG */
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#define DDR_PHY_REG0 0x0
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#define DDR_PHY_REG1 0x4
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#define DDR_PHY_REG2 0x8
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#define DDR_PHY_REG3 0xc
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#define DDR_PHY_REG4 0x10
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#define DDR_PHY_REG5 0x14
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#define DDR_PHY_REG6 0x18
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#define DDR_PHY_REGB 0x2c
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#define DDR_PHY_REGC 0x30
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#define DDR_PHY_REG11 0x44
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#define DDR_PHY_REG12 0x48
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#define DDR_PHY_REG13 0x4c
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#define DDR_PHY_REG14 0x50
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#define DDR_PHY_REG16 0x58
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#define DDR_PHY_REG20 0x80
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#define DDR_PHY_REG21 0x84
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#define DDR_PHY_REG26 0x98
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#define DDR_PHY_REG27 0x9c
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#define DDR_PHY_REG28 0xa0
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#define DDR_PHY_REG2C 0xb0
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#define DDR_PHY_REG30 0xc0
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#define DDR_PHY_REG31 0xc4
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#define DDR_PHY_REG36 0xd8
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#define DDR_PHY_REG37 0xdc
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#define DDR_PHY_REG38 0xe0
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#define DDR_PHY_REG3C 0xf0
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#define DDR_PHY_REG40 0x100
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#define DDR_PHY_REG41 0x104
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#define DDR_PHY_REG46 0x118
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#define DDR_PHY_REG47 0x11c
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#define DDR_PHY_REG48 0x120
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#define DDR_PHY_REG4C 0x130
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#define DDR_PHY_REG50 0x140
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#define DDR_PHY_REG51 0x144
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#define DDR_PHY_REG56 0x158
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#define DDR_PHY_REG57 0x15c
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#define DDR_PHY_REG58 0x160
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#define DDR_PHY_REG5C 0x170
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#define DDR_PHY_REGDLL 0x290
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#define DDR_PHY_REGEC 0x3b0
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#define DDR_PHY_REGED 0x3b4
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#define DDR_PHY_REGEE 0x3b8
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#define DDR_PHY_REGEF 0x3bc
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#define DDR_PHY_REGF0 0x3c0
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#define DDR_PHY_REGF1 0x3c4
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#define DDR_PHY_REGF2 0x3c8
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#define DDR_PHY_REGFA 0x3e8
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#define DDR_PHY_REGFB 0x3ec
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#define DDR_PHY_REGFC 0x3f0
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#define DDR_PHY_REGFD 0x3f4
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#define DDR_PHY_REGFE 0x3f8
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#define DDR_PHY_REGFF 0x3fc
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/* MSCH REG define */
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#define MSCH_COREID 0x0
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#define MSCH_DDRCONF 0x8
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#define MSCH_DDRTIMING 0xc
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#define MSCH_DDRMODE 0x10
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#define MSCH_READLATENCY 0x14
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#define MSCH_ACTIVATE 0x38
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#define MSCH_DEVTODEV 0x3c
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#define SET_NR(n) ((0x3f << (8 + 16)) | ((n - 1) << 8))
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#define SET_NO(n) ((0xf << (0 + 16)) | ((n - 1) << 0))
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#define SET_NF(n) ((n - 1) & 0x1fff)
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#define SET_NB(n) ((n - 1) & 0xfff)
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#define PLLMODE(n) ((0x3 << (8 + 16)) | (n << 8))
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/* GRF REG define */
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#define GRF_SOC_STATUS0 0x480
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#define GRF_DDRPHY_LOCK (0x1 << 15)
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#define GRF_DDRC0_CON0 0x600
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/* CRU softreset ddr pctl, phy */
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#define DDRMSCH0_SRSTN_REQ(n) (((0x1 << 10) << 16) | (n << 10))
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#define DDRCTRL0_PSRSTN_REQ(n) (((0x1 << 3) << 16) | (n << 3))
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#define DDRCTRL0_SRSTN_REQ(n) (((0x1 << 2) << 16) | (n << 2))
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#define DDRPHY0_PSRSTN_REQ(n) (((0x1 << 1) << 16) | (n << 1))
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#define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0))
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/* CRU_DPLL_CON2 */
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#define DPLL_STATUS_LOCK (1U << 31)
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/* CRU_DPLL_CON3 */
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#define DPLL_POWER_DOWN ((0x1 << (1 + 16)) | (0 << 1))
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#define DPLL_WORK_NORMAL_MODE ((0x3 << (8 + 16)) | (0 << 8))
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#define DPLL_WORK_SLOW_MODE ((0x3 << (8 + 16)) | (1 << 8))
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#define DPLL_RESET_CONTROL_NORMAL ((0x1 << (5 + 16)) | (0x0 << 5))
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#define DPLL_RESET_CONTROL_RESET ((0x1 << (5 + 16)) | (0x1 << 5))
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/* PMU_PWRDN_CON */
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#define PD_PERI_PWRDN_ENABLE (1 << 13)
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#define DDR_PLL_SRC_MASK 0x13
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/* DDR_PCTL_TREFI */
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#define DDR_UPD_REF_ENABLE (0X1u << 31)
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uint32_t ddr_get_resume_code_size(void);
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uint32_t ddr_get_resume_data_size(void);
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uint32_t *ddr_get_resume_code_base(void);
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void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr);
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#endif /* DDR_RK3368_H */
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