mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 02:24:18 +00:00
79ca7807cc
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
482 lines
15 KiB
C
482 lines
15 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <string.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <ddr_rk3368.h>
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#include <pmu.h>
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#include <rk3368_def.h>
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#include <soc.h>
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/* GRF_SOC_STATUS0 */
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#define DPLL_LOCK (0x1 << 2)
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/* GRF_DDRC0_CON0 */
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#define GRF_DDR_16BIT_EN (((0x1 << 3) << 16) | (0x1 << 3))
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#define GRF_DDR_32BIT_EN (((0x1 << 3) << 16) | (0x0 << 3))
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#define GRF_MOBILE_DDR_EN (((0x1 << 4) << 16) | (0x1 << 4))
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#define GRF_MOBILE_DDR_DISB (((0x1 << 4) << 16) | (0x0 << 4))
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#define GRF_DDR3_EN (((0x1 << 2) << 16) | (0x1 << 2))
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#define GRF_LPDDR2_3_EN (((0x1 << 2) << 16) | (0x0 << 2))
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/* PMUGRF_SOC_CON0 */
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#define ddrphy_bufferen_io_en(n) ((0x1 << (9 + 16)) | (n << 9))
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#define ddrphy_bufferen_core_en(n) ((0x1 << (8 + 16)) | (n << 8))
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struct PCTRL_TIMING_TAG {
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uint32_t ddrfreq;
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uint32_t TOGCNT1U;
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uint32_t TINIT;
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uint32_t TRSTH;
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uint32_t TOGCNT100N;
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uint32_t TREFI;
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uint32_t TMRD;
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uint32_t TRFC;
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uint32_t TRP;
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uint32_t TRTW;
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uint32_t TAL;
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uint32_t TCL;
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uint32_t TCWL;
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uint32_t TRAS;
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uint32_t TRC;
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uint32_t TRCD;
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uint32_t TRRD;
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uint32_t TRTP;
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uint32_t TWR;
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uint32_t TWTR;
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uint32_t TEXSR;
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uint32_t TXP;
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uint32_t TXPDLL;
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uint32_t TZQCS;
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uint32_t TZQCSI;
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uint32_t TDQS;
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uint32_t TCKSRE;
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uint32_t TCKSRX;
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uint32_t TCKE;
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uint32_t TMOD;
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uint32_t TRSTL;
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uint32_t TZQCL;
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uint32_t TMRR;
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uint32_t TCKESR;
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uint32_t TDPD;
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uint32_t TREFI_MEM_DDR3;
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};
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struct MSCH_SAVE_REG_TAG {
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uint32_t ddrconf;
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uint32_t ddrtiming;
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uint32_t ddrmode;
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uint32_t readlatency;
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uint32_t activate;
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uint32_t devtodev;
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};
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/* ddr suspend need save reg */
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struct PCTL_SAVE_REG_TAG {
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uint32_t SCFG;
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uint32_t CMDTSTATEN;
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uint32_t MCFG1;
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uint32_t MCFG;
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uint32_t PPCFG;
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struct PCTRL_TIMING_TAG pctl_timing;
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/* DFI Control Registers */
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uint32_t DFITCTRLDELAY;
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uint32_t DFIODTCFG;
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uint32_t DFIODTCFG1;
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uint32_t DFIODTRANKMAP;
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/* DFI Write Data Registers */
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uint32_t DFITPHYWRDATA;
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uint32_t DFITPHYWRLAT;
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uint32_t DFITPHYWRDATALAT;
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/* DFI Read Data Registers */
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uint32_t DFITRDDATAEN;
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uint32_t DFITPHYRDLAT;
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/* DFI Update Registers */
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uint32_t DFITPHYUPDTYPE0;
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uint32_t DFITPHYUPDTYPE1;
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uint32_t DFITPHYUPDTYPE2;
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uint32_t DFITPHYUPDTYPE3;
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uint32_t DFITCTRLUPDMIN;
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uint32_t DFITCTRLUPDMAX;
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uint32_t DFITCTRLUPDDLY;
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uint32_t DFIUPDCFG;
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uint32_t DFITREFMSKI;
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uint32_t DFITCTRLUPDI;
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/* DFI Status Registers */
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uint32_t DFISTCFG0;
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uint32_t DFISTCFG1;
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uint32_t DFITDRAMCLKEN;
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uint32_t DFITDRAMCLKDIS;
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uint32_t DFISTCFG2;
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/* DFI Low Power Register */
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uint32_t DFILPCFG0;
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};
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struct DDRPHY_SAVE_REG_TAG {
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uint32_t PHY_REG0;
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uint32_t PHY_REG1;
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uint32_t PHY_REGB;
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uint32_t PHY_REGC;
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uint32_t PHY_REG11;
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uint32_t PHY_REG13;
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uint32_t PHY_REG14;
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uint32_t PHY_REG16;
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uint32_t PHY_REG20;
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uint32_t PHY_REG21;
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uint32_t PHY_REG26;
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uint32_t PHY_REG27;
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uint32_t PHY_REG28;
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uint32_t PHY_REG30;
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uint32_t PHY_REG31;
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uint32_t PHY_REG36;
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uint32_t PHY_REG37;
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uint32_t PHY_REG38;
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uint32_t PHY_REG40;
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uint32_t PHY_REG41;
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uint32_t PHY_REG46;
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uint32_t PHY_REG47;
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uint32_t PHY_REG48;
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uint32_t PHY_REG50;
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uint32_t PHY_REG51;
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uint32_t PHY_REG56;
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uint32_t PHY_REG57;
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uint32_t PHY_REG58;
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uint32_t PHY_REGDLL;
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uint32_t PHY_REGEC;
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uint32_t PHY_REGED;
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uint32_t PHY_REGEE;
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uint32_t PHY_REGEF;
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uint32_t PHY_REGFB;
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uint32_t PHY_REGFC;
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uint32_t PHY_REGFD;
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uint32_t PHY_REGFE;
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};
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struct BACKUP_REG_TAG {
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uint32_t tag;
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uint32_t pctladdr;
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struct PCTL_SAVE_REG_TAG pctl;
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uint32_t phyaddr;
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struct DDRPHY_SAVE_REG_TAG phy;
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uint32_t nocaddr;
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struct MSCH_SAVE_REG_TAG noc;
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uint32_t pllselect;
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uint32_t phypllockaddr;
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uint32_t phyplllockmask;
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uint32_t phyplllockval;
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uint32_t pllpdstat;
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uint32_t dpllmodeaddr;
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uint32_t dpllslowmode;
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uint32_t dpllnormalmode;
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uint32_t dpllresetaddr;
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uint32_t dpllreset;
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uint32_t dplldereset;
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uint32_t dpllconaddr;
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uint32_t dpllcon[4];
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uint32_t dplllockaddr;
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uint32_t dplllockmask;
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uint32_t dplllockval;
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uint32_t ddrpllsrcdivaddr;
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uint32_t ddrpllsrcdiv;
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uint32_t retendisaddr;
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uint32_t retendisval;
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uint32_t grfregaddr;
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uint32_t grfddrcreg;
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uint32_t crupctlphysoftrstaddr;
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uint32_t cruresetpctlphy;
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uint32_t cruderesetphy;
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uint32_t cruderesetpctlphy;
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uint32_t physoftrstaddr;
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uint32_t endtag;
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};
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static uint32_t ddr_get_phy_pll_freq(void)
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{
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uint32_t ret = 0;
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uint32_t fb_div, pre_div;
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fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
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fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8;
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pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff;
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ret = 2 * 24 * fb_div / (4 * pre_div);
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return ret;
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}
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static void ddr_copy(uint32_t *pdest, uint32_t *psrc, uint32_t words)
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{
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uint32_t i;
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for (i = 0; i < words; i++)
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pdest[i] = psrc[i];
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}
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static void ddr_get_dpll_cfg(uint32_t *p)
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{
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uint32_t nmhz, NO, NF, NR;
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nmhz = ddr_get_phy_pll_freq();
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if (nmhz <= 150)
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NO = 6;
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else if (nmhz <= 250)
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NO = 4;
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else if (nmhz <= 500)
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NO = 2;
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else
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NO = 1;
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NR = 1;
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NF = 2 * nmhz * NR * NO / 24;
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p[0] = SET_NR(NR) | SET_NO(NO);
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p[1] = SET_NF(NF);
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p[2] = SET_NB(NF / 2);
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}
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void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
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{
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struct BACKUP_REG_TAG *p_ddr_reg = (struct BACKUP_REG_TAG *)base_addr;
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struct PCTL_SAVE_REG_TAG *pctl_tim = &p_ddr_reg->pctl;
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p_ddr_reg->tag = 0x56313031;
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p_ddr_reg->pctladdr = DDR_PCTL_BASE;
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p_ddr_reg->phyaddr = DDR_PHY_BASE;
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p_ddr_reg->nocaddr = SERVICE_BUS_BASE;
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/* PCTLR */
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ddr_copy((uint32_t *)&pctl_tim->pctl_timing.TOGCNT1U,
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(uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35);
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pctl_tim->pctl_timing.TREFI |= DDR_UPD_REF_ENABLE;
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pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG);
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pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_CMDTSTATEN);
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pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1);
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pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG);
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pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG);
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pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_TOGCNT1U * 2);
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pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITCTRLDELAY);
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pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG);
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pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFIODTCFG1);
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pctl_tim->DFIODTRANKMAP = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFIODTRANKMAP);
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pctl_tim->DFITPHYWRDATA = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYWRDATA);
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pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYWRLAT);
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pctl_tim->DFITPHYWRDATALAT = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYWRDATALAT);
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pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITRDDATAEN);
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pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYRDLAT);
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pctl_tim->DFITPHYUPDTYPE0 = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYUPDTYPE0);
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pctl_tim->DFITPHYUPDTYPE1 = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYUPDTYPE1);
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pctl_tim->DFITPHYUPDTYPE2 = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYUPDTYPE2);
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pctl_tim->DFITPHYUPDTYPE3 = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITPHYUPDTYPE3);
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pctl_tim->DFITCTRLUPDMIN = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITCTRLUPDMIN);
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pctl_tim->DFITCTRLUPDMAX = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITCTRLUPDMAX);
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pctl_tim->DFITCTRLUPDDLY = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITCTRLUPDDLY);
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pctl_tim->DFIUPDCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIUPDCFG);
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pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITREFMSKI);
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pctl_tim->DFITCTRLUPDI = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITCTRLUPDI);
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pctl_tim->DFISTCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG0);
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pctl_tim->DFISTCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG1);
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pctl_tim->DFITDRAMCLKEN = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITDRAMCLKEN);
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pctl_tim->DFITDRAMCLKDIS = mmio_read_32(DDR_PCTL_BASE +
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DDR_PCTL_DFITDRAMCLKDIS);
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pctl_tim->DFISTCFG2 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG2);
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pctl_tim->DFILPCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFILPCFG0);
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/* PHY */
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p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0);
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p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1);
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p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB);
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p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC);
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p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11);
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p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13);
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p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14);
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p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16);
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p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20);
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p_ddr_reg->phy.PHY_REG21 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG21);
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p_ddr_reg->phy.PHY_REG26 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG26);
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p_ddr_reg->phy.PHY_REG27 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG27);
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p_ddr_reg->phy.PHY_REG28 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG28);
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p_ddr_reg->phy.PHY_REG30 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG30);
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p_ddr_reg->phy.PHY_REG31 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG31);
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p_ddr_reg->phy.PHY_REG36 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG36);
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p_ddr_reg->phy.PHY_REG37 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG37);
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p_ddr_reg->phy.PHY_REG38 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG38);
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p_ddr_reg->phy.PHY_REG40 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG40);
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p_ddr_reg->phy.PHY_REG41 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG41);
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p_ddr_reg->phy.PHY_REG46 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG46);
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p_ddr_reg->phy.PHY_REG47 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG47);
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p_ddr_reg->phy.PHY_REG48 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG48);
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p_ddr_reg->phy.PHY_REG50 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG50);
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p_ddr_reg->phy.PHY_REG51 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG51);
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p_ddr_reg->phy.PHY_REG56 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG56);
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p_ddr_reg->phy.PHY_REG57 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG57);
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p_ddr_reg->phy.PHY_REG58 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG58);
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p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REGDLL);
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p_ddr_reg->phy.PHY_REGEC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
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p_ddr_reg->phy.PHY_REGED = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED);
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p_ddr_reg->phy.PHY_REGEE = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE);
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p_ddr_reg->phy.PHY_REGEF = 0;
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if (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG2) & 0x2) {
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p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REG2C);
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p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REG3C);
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p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REG4C);
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p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REG5C);
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} else {
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p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REGFB);
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p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REGFC);
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p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REGFD);
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p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
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DDR_PHY_REGFE);
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}
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/* NOC */
|
|
p_ddr_reg->noc.ddrconf = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRCONF);
|
|
p_ddr_reg->noc.ddrtiming = mmio_read_32(SERVICE_BUS_BASE +
|
|
MSCH_DDRTIMING);
|
|
p_ddr_reg->noc.ddrmode = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRMODE);
|
|
p_ddr_reg->noc.readlatency = mmio_read_32(SERVICE_BUS_BASE +
|
|
MSCH_READLATENCY);
|
|
p_ddr_reg->noc.activate = mmio_read_32(SERVICE_BUS_BASE +
|
|
MSCH_ACTIVATE);
|
|
p_ddr_reg->noc.devtodev = mmio_read_32(SERVICE_BUS_BASE +
|
|
MSCH_DEVTODEV);
|
|
|
|
p_ddr_reg->pllselect = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) * 0x1;
|
|
p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0;
|
|
p_ddr_reg->phyplllockmask = GRF_DDRPHY_LOCK;
|
|
p_ddr_reg->phyplllockval = 0;
|
|
|
|
/* PLLPD */
|
|
p_ddr_reg->pllpdstat = pllpdstat;
|
|
/* DPLL */
|
|
p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
|
|
/* slow mode and power on */
|
|
p_ddr_reg->dpllslowmode = DPLL_WORK_SLOW_MODE | DPLL_POWER_DOWN;
|
|
p_ddr_reg->dpllnormalmode = DPLL_WORK_NORMAL_MODE;
|
|
p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
|
|
p_ddr_reg->dpllreset = DPLL_RESET_CONTROL_NORMAL;
|
|
p_ddr_reg->dplldereset = DPLL_RESET_CONTROL_RESET;
|
|
p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0);
|
|
|
|
if (p_ddr_reg->pllselect == 0) {
|
|
p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
|
|
PLL_CONS(DPLL_ID, 0))
|
|
& 0xffff) |
|
|
(0xFFFFu << 16);
|
|
p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
|
|
PLL_CONS(DPLL_ID, 1))
|
|
& 0xffff);
|
|
p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE +
|
|
PLL_CONS(DPLL_ID, 2))
|
|
& 0xffff);
|
|
p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
|
|
PLL_CONS(DPLL_ID, 3))
|
|
& 0xffff) |
|
|
(0xFFFFu << 16);
|
|
} else {
|
|
ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
|
|
}
|
|
|
|
p_ddr_reg->pllselect = 0;
|
|
p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1);
|
|
p_ddr_reg->dplllockmask = DPLL_STATUS_LOCK;
|
|
p_ddr_reg->dplllockval = DPLL_STATUS_LOCK;
|
|
|
|
/* SET_DDR_PLL_SRC */
|
|
p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13);
|
|
p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13))
|
|
& DDR_PLL_SRC_MASK)
|
|
| (DDR_PLL_SRC_MASK << 16);
|
|
p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM;
|
|
p_ddr_reg->retendisval = PD_PERI_PWRDN_ENABLE;
|
|
p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0;
|
|
p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) &
|
|
DDR_PLL_SRC_MASK) |
|
|
(DDR_PLL_SRC_MASK << 16);
|
|
|
|
/* pctl phy soft reset */
|
|
p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10);
|
|
p_ddr_reg->cruresetpctlphy = DDRCTRL0_PSRSTN_REQ(1) |
|
|
DDRCTRL0_SRSTN_REQ(1) |
|
|
DDRPHY0_PSRSTN_REQ(1) |
|
|
DDRPHY0_SRSTN_REQ(1);
|
|
p_ddr_reg->cruderesetphy = DDRCTRL0_PSRSTN_REQ(1) |
|
|
DDRCTRL0_SRSTN_REQ(1) |
|
|
DDRPHY0_PSRSTN_REQ(0) |
|
|
DDRPHY0_SRSTN_REQ(0);
|
|
|
|
p_ddr_reg->cruderesetpctlphy = DDRCTRL0_PSRSTN_REQ(0) |
|
|
DDRCTRL0_SRSTN_REQ(0) |
|
|
DDRPHY0_PSRSTN_REQ(0) |
|
|
DDRPHY0_SRSTN_REQ(0);
|
|
|
|
p_ddr_reg->physoftrstaddr = DDR_PHY_BASE + DDR_PHY_REG0;
|
|
|
|
p_ddr_reg->endtag = 0xFFFFFFFF;
|
|
}
|
|
|
|
/*
|
|
* "rk3368_ddr_reg_resume_V1.05.bin" is an executable bin which is generated
|
|
* by ARM DS5 for resuming ddr controller. If the soc wakes up from system
|
|
* suspend, ddr needs to be resumed and the resuming code needs to be run in
|
|
* sram. But there is not a way to pointing the resuming code to the PMUSRAM
|
|
* when linking .o files of bl31, so we use the
|
|
* "rk3368_ddr_reg_resume_V1.05.bin" whose code is position-independent and
|
|
* it can be loaded anywhere and run.
|
|
*/
|
|
static __aligned(4) unsigned int ddr_reg_resume[] = {
|
|
#include "rk3368_ddr_reg_resume_V1.05.bin"
|
|
};
|
|
|
|
uint32_t ddr_get_resume_code_size(void)
|
|
{
|
|
return sizeof(ddr_reg_resume);
|
|
}
|
|
|
|
uint32_t ddr_get_resume_data_size(void)
|
|
{
|
|
return sizeof(struct BACKUP_REG_TAG);
|
|
}
|
|
|
|
uint32_t *ddr_get_resume_code_base(void)
|
|
{
|
|
return (unsigned int *)ddr_reg_resume;
|
|
}
|