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https://github.com/ARM-software/arm-trusted-firmware.git
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621d5f2a5b
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: If5a88e1b880bcb2be2278398cf5109a6d877e632 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
247 lines
7 KiB
C
247 lines
7 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT8183_MCUCFG_H
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#define MT8183_MCUCFG_H
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#include <platform_def.h>
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#include <stdint.h>
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struct mt8183_mcucfg_regs {
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uint32_t mp0_ca7l_cache_config; /* 0x0 */
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struct {
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uint32_t mem_delsel0;
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uint32_t mem_delsel1;
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} mp0_cpu[4]; /* 0x4 */
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uint32_t mp0_cache_mem_delsel0; /* 0x24 */
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uint32_t mp0_cache_mem_delsel1; /* 0x28 */
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uint32_t mp0_axi_config; /* 0x2C */
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uint32_t mp0_misc_config[10]; /* 0x30 */
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uint32_t mp0_ca7l_cfg_dis; /* 0x58 */
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uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */
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uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */
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uint32_t mp0_ca7l_misc_config; /* 0x64 */
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uint32_t mp0_ca7l_dbg_pwr_ctrl; /* 0x68 */
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uint32_t mp0_rw_rsvd0; /* 0x6C */
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uint32_t mp0_rw_rsvd1; /* 0x70 */
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uint32_t mp0_ro_rsvd; /* 0x74 */
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uint32_t reserved0_0[98]; /* 0x78 */
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uint32_t mp1_ca7l_cache_config; /* 0x200 */
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uint32_t mp1_miscdbg; /* 0x204 */
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uint32_t reserved0_1[9]; /* 0x208 */
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uint32_t mp1_axi_config; /* 0x22C */
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uint32_t mp1_misc_config[10]; /* 0x230 */
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uint32_t reserved0_2[3]; /* 0x258 */
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uint32_t mp1_ca7l_misc_config; /* 0x264 */
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uint32_t reserved0_3[310]; /* 0x268 */
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uint32_t cci_adb400_dcm_config; /* 0x740 */
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uint32_t sync_dcm_config; /* 0x744 */
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uint32_t reserved0_4[16]; /* 0x748 */
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uint32_t mp0_cputop_spmc_ctl; /* 0x788 */
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uint32_t mp1_cputop_spmc_ctl; /* 0x78C */
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uint32_t mp1_cputop_spmc_sram_ctl; /* 0x790 */
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uint32_t reserved0_5[23]; /* 0x794 */
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uint32_t l2_cfg_mp0; /* 0x7F0 */
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uint32_t l2_cfg_mp1; /* 0x7F4 */
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uint32_t reserved0_6[1282]; /* 0x7F8 */
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uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */
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uint32_t cpusys0_sparken; /* 0x1C04 */
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uint32_t cpusys0_amuxsel; /* 0x1C08 */
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uint32_t reserved0_7[9]; /* 0x1C0C */
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uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */
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uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */
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uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */
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uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */
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uint32_t reserved0_8[370]; /* 0x1C40 */
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uint32_t mp2_cpucfg; /* 0x2208 */
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uint32_t mp2_axi_config; /* 0x220C */
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uint32_t reserved0_9[36]; /* 0x2210 */
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uint32_t mp2_cputop_spm_ctl; /* 0x22A0 */
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uint32_t mp2_cputop_spm_sta; /* 0x22A4 */
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uint32_t reserved0_10[98]; /* 0x22A8 */
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uint32_t cpusys2_cpu0_spmc_ctl; /* 0x2430 */
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uint32_t cpusys2_cpu0_spmc_sta; /* 0x2434 */
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uint32_t cpusys2_cpu1_spmc_ctl; /* 0x2438 */
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uint32_t cpusys2_cpu1_spmc_sta; /* 0x243C */
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uint32_t reserved0_11[176]; /* 0x2440 */
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uint32_t spark2ld0; /* 0x2700 */
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uint32_t reserved0_12[1355]; /* 0x2704 */
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uint32_t cpusys1_cpu0_spmc_ctl; /* 0x3C30 */
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uint32_t cpusys1_cpu1_spmc_ctl; /* 0x3C34 */
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uint32_t cpusys1_cpu2_spmc_ctl; /* 0x3C38 */
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uint32_t cpusys1_cpu3_spmc_ctl; /* 0x3C3C */
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};
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static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
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enum {
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SW_SPARK_EN = 1 << 0,
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SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
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SW_FSM_OVERRIDE = 1 << 2,
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SW_LOGIC_PRE1_PDB = 1 << 3,
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SW_LOGIC_PRE2_PDB = 1 << 4,
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SW_LOGIC_PDB = 1 << 5,
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SW_ISO = 1 << 6,
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SW_SRAM_SLEEPB = 0x3f << 7,
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SW_SRAM_ISOINTB = 1 << 13,
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SW_CLK_DIS = 1 << 14,
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SW_CKISO = 1 << 15,
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SW_PD = 0x3f << 16,
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SW_HOT_PLUG_RESET = 1 << 22,
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SW_PWR_ON_OVERRIDE_EN = 1 << 23,
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SW_PWR_ON = 1 << 24,
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SW_COQ_DIS = 1 << 25,
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LOGIC_PDBO_ALL_OFF_ACK = 1 << 26,
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LOGIC_PDBO_ALL_ON_ACK = 1 << 27,
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LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 28,
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LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 29
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};
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enum {
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CPU_SW_SPARK_EN = 1 << 0,
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CPU_SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
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CPU_SW_FSM_OVERRIDE = 1 << 2,
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CPU_SW_LOGIC_PRE1_PDB = 1 << 3,
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CPU_SW_LOGIC_PRE2_PDB = 1 << 4,
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CPU_SW_LOGIC_PDB = 1 << 5,
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CPU_SW_ISO = 1 << 6,
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CPU_SW_SRAM_SLEEPB = 1 << 7,
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CPU_SW_SRAM_ISOINTB = 1 << 8,
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CPU_SW_CLK_DIS = 1 << 9,
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CPU_SW_CKISO = 1 << 10,
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CPU_SW_PD = 0x1f << 11,
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CPU_SW_HOT_PLUG_RESET = 1 << 16,
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CPU_SW_POWR_ON_OVERRIDE_EN = 1 << 17,
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CPU_SW_PWR_ON = 1 << 18,
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CPU_SPARK2LDO_ALLSWOFF = 1 << 19,
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CPU_PDBO_ALL_ON_ACK = 1 << 20,
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CPU_PRE2_PDBO_ALLON_ACK = 1 << 21,
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CPU_PRE1_PDBO_ALLON_ACK = 1 << 22
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};
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enum {
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MP2_AXI_CONFIG_ACINACTM = 1 << 0,
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MPx_AXI_CONFIG_ACINACTM = 1 << 4,
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MPX_CA7_MISC_CONFIG_STANDBYWFIL2 = 1 << 28
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};
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enum {
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MP0_CPU0_STANDBYWFE = 1 << 20,
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MP0_CPU1_STANDBYWFE = 1 << 21,
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MP0_CPU2_STANDBYWFE = 1 << 22,
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MP0_CPU3_STANDBYWFE = 1 << 23
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};
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enum {
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MP1_CPU0_STANDBYWFE = 1 << 20,
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MP1_CPU1_STANDBYWFE = 1 << 21,
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MP1_CPU2_STANDBYWFE = 1 << 22,
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MP1_CPU3_STANDBYWFE = 1 << 23
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};
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enum {
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B_SW_HOT_PLUG_RESET = 1 << 30,
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B_SW_PD_OFFSET = 18,
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B_SW_PD = 0x3f << B_SW_PD_OFFSET,
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B_SW_SRAM_SLEEPB_OFFSET = 12,
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B_SW_SRAM_SLEEPB = 0x3f << B_SW_SRAM_SLEEPB_OFFSET
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};
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enum {
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B_SW_SRAM_ISOINTB = 1 << 9,
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B_SW_ISO = 1 << 8,
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B_SW_LOGIC_PDB = 1 << 7,
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B_SW_LOGIC_PRE2_PDB = 1 << 6,
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B_SW_LOGIC_PRE1_PDB = 1 << 5,
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B_SW_FSM_OVERRIDE = 1 << 4,
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B_SW_PWR_ON = 1 << 3,
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B_SW_PWR_ON_OVERRIDE_EN = 1 << 2
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};
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enum {
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B_FSM_STATE_OUT_OFFSET = 6,
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B_FSM_STATE_OUT_MASK = 0x1f << B_FSM_STATE_OUT_OFFSET,
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B_SW_LOGIC_PDBO_ALL_OFF_ACK = 1 << 5,
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B_SW_LOGIC_PDBO_ALL_ON_ACK = 1 << 4,
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B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 3,
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B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 2,
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B_FSM_OFF = 0 << B_FSM_STATE_OUT_OFFSET,
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B_FSM_ON = 1 << B_FSM_STATE_OUT_OFFSET,
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B_FSM_RET = 2 << B_FSM_STATE_OUT_OFFSET
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};
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/* APB Module infracfg_ao */
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enum {
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INFRA_TOPAXI_PROTECTEN_1 = INFRACFG_AO_BASE + 0x250,
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INFRA_TOPAXI_PROTECTSTA1_1 = INFRACFG_AO_BASE + 0x258,
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INFRA_TOPAXI_PROTECTEN_1_SET = INFRACFG_AO_BASE + 0x2A8,
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INFRA_TOPAXI_PROTECTEN_1_CLR = INFRACFG_AO_BASE + 0x2AC
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};
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enum {
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IDX_PROTECT_MP0_CACTIVE = 10,
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IDX_PROTECT_MP1_CACTIVE = 11,
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IDX_PROTECT_ICC0_CACTIVE = 12,
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IDX_PROTECT_ICD0_CACTIVE = 13,
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IDX_PROTECT_ICC1_CACTIVE = 14,
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IDX_PROTECT_ICD1_CACTIVE = 15,
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IDX_PROTECT_L2C0_CACTIVE = 26,
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IDX_PROTECT_L2C1_CACTIVE = 27
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};
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/* cpu boot mode */
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enum {
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MP0_CPUCFG_64BIT_SHIFT = 12,
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MP1_CPUCFG_64BIT_SHIFT = 28,
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MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
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MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT
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};
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/* scu related */
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enum {
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MP0_ACINACTM_SHIFT = 4,
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MP1_ACINACTM_SHIFT = 4,
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MP2_ACINACTM_SHIFT = 0,
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MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
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MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT,
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MP2_ACINACTM = 1 << MP2_ACINACTM_SHIFT
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};
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enum {
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
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};
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enum {
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MP1_AINACTS_SHIFT = 4,
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MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
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};
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enum {
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MP1_SW_CG_GEN_SHIFT = 12,
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MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
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};
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enum {
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MP1_L2RSTDISABLE_SHIFT = 14,
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MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
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};
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#endif /* MT8183_MCUCFG_H */
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