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https://github.com/ARM-software/arm-trusted-firmware.git
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621d5f2a5b
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: If5a88e1b880bcb2be2278398cf5109a6d877e632 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCSI_H
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#define MCSI_H
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#define SLAVE_IFACE7_OFFSET 0x1700
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#define SLAVE_IFACE6_OFFSET 0x1600
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#define SLAVE_IFACE5_OFFSET 0x1500
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#define SLAVE_IFACE4_OFFSET 0x1400
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#define SLAVE_IFACE3_OFFSET 0x1300
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#define SLAVE_IFACE2_OFFSET 0x1200
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#define SLAVE_IFACE1_OFFSET 0x1100
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#define SLAVE_IFACE0_OFFSET 0x1000
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#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
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(0x100 * (index)))
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/* Control and ID register offsets */
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#define CENTRAL_CTRL_REG 0x0
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#define ERR_FLAG_REG 0x4
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#define SF_INIT_REG 0x10
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#define SF_CTRL_REG 0x14
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#define DCM_CTRL_REG 0x18
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#define ERR_FLAG2_REG 0x20
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#define SNP_PENDING_REG 0x28
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#define ACP_PENDING_REG 0x2c
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#define FLUSH_SF 0x500
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#define SYS_CCE_CTRL 0x2000
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#define MST1_CTRL 0x2100
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#define MTS2_CTRL 0x2200
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#define XBAR_ARAW_ARB 0x3000
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#define XBAR_R_ARB 0x3004
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/* Slave interface register offsets */
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#define SNOOP_CTRL_REG 0x0
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#define QOS_CTRL_REG 0x4
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#define QOS_OVERRIDE_REG 0x8
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#define QOS_TARGET_REG 0xc
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#define BD_CTRL_REG 0x40
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/* Snoop Control register bit definitions */
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#define DVM_SUPPORT (1U << 31)
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#define SNP_SUPPORT (1 << 30)
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#define SHAREABLE_OVWRT (1 << 2)
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#define DVM_EN_BIT (1 << 1)
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#define SNOOP_EN_BIT (1 << 0)
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#define SF2_INIT_DONE (1 << 17)
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#define SF1_INIT_DONE (1 << 16)
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#define TRIG_SF2_INIT (1 << 1)
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#define TRIG_SF1_INIT (1 << 0)
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/* Status register bit definitions */
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#define SNP_PENDING 31
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/* Status bit */
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#define NS_ACC 1
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#define S_ACC 0
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/* Central control register bit definitions */
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#define PMU_SECURE_ACC_EN (1 << 4)
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#define INT_EN (1 << 3)
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#define SECURE_ACC_EN (1 << 2)
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#define DVM_DIS (1 << 1)
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#define SNOOP_DIS (1 << 0)
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#define MSCI_MEMORY_SZ (0x10000)
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#define MCSI_REG_ACCESS_READ (0x0)
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#define MCSI_REG_ACCESS_WRITE (0x1)
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#define MCSI_REG_ACCESS_SET_BITMASK (0x2)
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#define MCSI_REG_ACCESS_CLEAR_BITMASK (0x3)
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#define NR_MAX_SLV (7)
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/* ICCS */
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#define CACHE_INSTR_EN (1 << 2)
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#define IDLE_CACHE (1 << 3)
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#define USE_SHARED_CACHE (1 << 4)
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#define CACHE_SHARED_PRE_EN (1 << 5)
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#define CACHE_SHARED_POST_EN (1 << 6)
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#define ACP_PENDING_MASK (0x1007f)
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#define CCI_CLK_CTRL (MCUCFG_BASE + 0x660)
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#ifndef __ASSEMBLY__
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#include <plat/common/common_def.h>
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#include <stdint.h>
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/* Function declarations */
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/*
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* The MCSI driver must be initialized with the base address of the
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* MCSI device in the platform memory map, and the cluster indices for
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* the MCSI slave interfaces 3 and 4 respectively. These are the fully
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* coherent ACE slave interfaces of MCSI.
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* The cluster indices must either be 0 or 1, corresponding to the level 1
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* affinity instance of the mpidr representing the cluster. A negative cluster
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* index indicates that no cluster is present on that slave interface.
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*/
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void mcsi_init(unsigned long cci_base,
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unsigned int num_cci_masters);
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void mcsi_cache_flush(void);
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void cci_enable_cluster_coherency(unsigned long mpidr);
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void cci_disable_cluster_coherency(unsigned long mpidr);
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void cci_secure_switch(unsigned int ns);
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void cci_init_sf(void);
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unsigned long cci_reg_access(unsigned int op, unsigned long offset, unsigned long val);
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#endif /* __ASSEMBLY__ */
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#endif /* MCSI_H */
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