mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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b19498b97b
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
194 lines
6.3 KiB
C
194 lines
6.3 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef A8K_PLAT_DEF_H
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#define A8K_PLAT_DEF_H
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#include <marvell_def.h>
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#define MVEBU_PRIMARY_CPU 0x0
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#define MVEBU_AP0 0x0
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/* APN806 revision ID */
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#define MVEBU_CSS_GWD_CTRL_IIDR2_REG (MVEBU_REGS_BASE + 0x610FCC)
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#define GWD_IIDR2_REV_ID_OFFSET 12
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#define GWD_IIDR2_REV_ID_MASK 0xF
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#define GWD_IIDR2_CHIP_ID_OFFSET 20
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#define GWD_IIDR2_CHIP_ID_MASK (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET)
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#define CHIP_ID_AP806 0x806
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#define CHIP_ID_AP807 0x807
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#define COUNTER_FREQUENCY 25000000
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#define MVEBU_REGS_BASE 0xF0000000
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#define MVEBU_REGS_BASE_MASK 0xF0000000
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#define MVEBU_REGS_BASE_AP(ap) MVEBU_REGS_BASE
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#define MVEBU_AP_IO_BASE(ap) 0xF2000000
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#define MVEBU_CP_OFFSET 0x2000000
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#define MVEBU_CP_REGS_BASE(cp_index) (MVEBU_AP_IO_BASE(0) + \
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(cp_index) * MVEBU_CP_OFFSET)
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#define MVEBU_RFU_BASE (MVEBU_REGS_BASE + 0x6F0000)
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#define MVEBU_IO_WIN_BASE(ap_index) (MVEBU_RFU_BASE)
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#define MVEBU_IO_WIN_GCR_OFFSET (0x70)
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#define MVEBU_IO_WIN_MAX_WINS (7)
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/* Misc SoC configurations Base */
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#define MVEBU_MISC_SOC_BASE (MVEBU_REGS_BASE + 0x6F4300)
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#define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000)
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#define MVEBU_CCU_MAX_WINS (8)
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#define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000)
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#define MVEBU_DRAM_MAC_BASE (MVEBU_REGS_BASE + 0x20000)
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#define MVEBU_DRAM_PHY_BASE (MVEBU_REGS_BASE + 0x20000)
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#define MVEBU_SMMU_BASE (MVEBU_REGS_BASE + 0x100000)
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#define MVEBU_CP_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
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0x440000 + ((n) << 2))
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#define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
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0x440000 + ((n / 8) << 2))
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#define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \
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(MVEBU_CP_REGS_BASE(cp_index) + \
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0x440100 + ((n > 31) ? 0x40 : 0x00))
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#define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \
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(MVEBU_CP_REGS_BASE(cp_index) + \
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0x440104 + ((n > 31) ? 0x40 : 0x00))
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#define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
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0x440110 + ((n > 31) ? 0x40 : 0x00))
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#define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2))
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#define MVEBU_AP_GPIO_REGS (MVEBU_RFU_BASE + 0x5040)
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#define MVEBU_AP_GPIO_DATA_IN (MVEBU_AP_GPIO_REGS + 0x10)
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#define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000)
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#define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000)
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#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084)
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#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \
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0x20080 + ((win) * 0x8))
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#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \
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0x20084 + ((win) * 0x8))
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/* MCI indirect access definitions */
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#define MCI_MAX_UNIT_ID 2
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/* SoC RFU / IHBx4 Control */
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#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \
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0x4218 + (unit_id * 0x20))
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#define MCI_REMAP_OFF_SHIFT 8
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#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + \
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((index) * 0x1000000))
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#define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000)
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#define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000)
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#define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000)
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#define MVEBU_CP_DFX_OFFSET (0x400200)
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/*****************************************************************************
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* MVEBU memory map related constants
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*****************************************************************************
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*/
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE MVEBU_REGS_BASE
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#define DEVICE0_SIZE 0x10000000
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/*****************************************************************************
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* GIC-400 & interrupt handling related constants
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*****************************************************************************
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*/
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/* Base MVEBU compatible GIC memory map */
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#define MVEBU_GICD_BASE 0x210000
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#define MVEBU_GICC_BASE 0x220000
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/*****************************************************************************
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* AXI Configuration
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*****************************************************************************
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*/
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#define MVEBU_AXI_ATTR_ARCACHE_OFFSET 4
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#define MVEBU_AXI_ATTR_ARCACHE_MASK (0xF << \
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MVEBU_AXI_ATTR_ARCACHE_OFFSET)
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#define MVEBU_AXI_ATTR_ARDOMAIN_OFFSET 12
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#define MVEBU_AXI_ATTR_ARDOMAIN_MASK (0x3 << \
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MVEBU_AXI_ATTR_ARDOMAIN_OFFSET)
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#define MVEBU_AXI_ATTR_AWCACHE_OFFSET 20
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#define MVEBU_AXI_ATTR_AWCACHE_MASK (0xF << \
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MVEBU_AXI_ATTR_AWCACHE_OFFSET)
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#define MVEBU_AXI_ATTR_AWDOMAIN_OFFSET 28
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#define MVEBU_AXI_ATTR_AWDOMAIN_MASK (0x3 << \
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MVEBU_AXI_ATTR_AWDOMAIN_OFFSET)
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/* SATA MBUS to AXI configuration */
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#define MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET 1
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#define MVEBU_SATA_M2A_AXI_ARCACHE_MASK (0xF << \
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MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET)
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#define MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET 5
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#define MVEBU_SATA_M2A_AXI_AWCACHE_MASK (0xF << \
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MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET)
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/* ARM cache attributes */
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#define CACHE_ATTR_BUFFERABLE 0x1
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#define CACHE_ATTR_CACHEABLE 0x2
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#define CACHE_ATTR_READ_ALLOC 0x4
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#define CACHE_ATTR_WRITE_ALLOC 0x8
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/* Domain */
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#define DOMAIN_NON_SHAREABLE 0x0
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#define DOMAIN_INNER_SHAREABLE 0x1
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#define DOMAIN_OUTER_SHAREABLE 0x2
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#define DOMAIN_SYSTEM_SHAREABLE 0x3
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/************************************************************************
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* Required platform porting definitions common to all
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* Management Compute SubSystems (MSS)
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************************************************************************
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*/
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/*
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* Load address of SCP_BL2
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* SCP_BL2 is loaded to the same place as BL31.
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* Once SCP_BL2 is transferred to the SCP,
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* it is discarded and BL31 is loaded over the top.
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*/
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#ifdef SCP_IMAGE
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#define SCP_BL2_BASE BL31_BASE
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#define SCP_BL2_SIZE BL31_LIMIT
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#endif
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#ifndef __ASSEMBLER__
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enum ap806_sar_target_dev {
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SAR_PIDI_MCIX2 = 0x0,
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SAR_MCIX4 = 0x1,
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SAR_SPI = 0x2,
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SAR_SD = 0x3,
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SAR_PIDI_MCIX2_BD = 0x4, /* BootRom disabled */
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SAR_MCIX4_DB = 0x5, /* BootRom disabled */
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SAR_SPI_DB = 0x6, /* BootRom disabled */
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SAR_EMMC = 0x7
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};
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enum io_win_target_ids {
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MCI_0_TID = 0x0,
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MCI_1_TID = 0x1,
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MCI_2_TID = 0x2,
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PIDI_TID = 0x3,
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SPI_TID = 0x4,
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STM_TID = 0x5,
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BOOTROM_TID = 0x6,
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IO_WIN_MAX_TID
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};
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enum ccu_target_ids {
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IO_0_TID = 0x00,
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DRAM_0_TID = 0x03,
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IO_1_TID = 0x0F,
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CFG_REG_TID = 0x10,
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RAR_TID = 0x20,
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SRAM_TID = 0x40,
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DRAM_1_TID = 0xC0,
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CCU_MAX_TID,
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INVALID_TID = 0xFF
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};
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#endif /* __ASSEMBLER__ */
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#endif /* A8K_PLAT_DEF_H */
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