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https://github.com/ARM-software/arm-trusted-firmware.git
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9e4afb0272
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib63ef6e2e4616dd56828bfd3800d5fe2df109934 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <endian.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "soc.h"
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/*
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* Get GIC offset
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* For LS1043a rev1.0, GIC base address align with 4k.
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* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
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* is set, GIC base address align with 4K, or else align
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* with 64k.
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*/
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void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
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{
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uint32_t *ccsr_svr = (uint32_t *)DCFG_CCSR_SVR;
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uint32_t *gic_align = (uint32_t *)SCFG_GIC400_ALIGN;
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uint32_t val;
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uint32_t soc_dev_id;
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val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
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soc_dev_id = val & (SVR_WO_E << 8);
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if ((soc_dev_id == (SVR_LS1043A << 8) ||
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soc_dev_id == (SVR_LS1043AE << 8)) &&
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((val & 0xff) == REV1_1)) {
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val = be32toh(mmio_read_32((uintptr_t)gic_align));
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if (val & (1U << GIC_ADDR_BIT)) {
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*gicc_base = GICC_BASE;
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*gicd_base = GICD_BASE;
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} else {
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*gicc_base = GICC_BASE_64K;
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*gicd_base = GICD_BASE_64K;
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}
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} else {
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*gicc_base = GICC_BASE;
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*gicd_base = GICD_BASE;
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}
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}
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