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36cfbf3ca2
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __S10_MBOX__
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#define __S10_MBOX__
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#define MBOX_OFFSET 0xffa30000
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#define MBOX_ATF_CLIENT_ID 0x1
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#define MBOX_JOB_ID 0x1
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/* Mailbox interrupt flags and masks */
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#define MBOX_INT_FLAG_COE 0x1
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#define MBOX_INT_FLAG_RIE 0x2
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#define MBOX_INT_FLAG_UAE 0x100
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#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
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#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<4)))
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/* Mailbox response and status */
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
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#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
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#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
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#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
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#define MBOX_STATUS_UA_MASK (1<<8)
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/* Mailbox command and response */
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#define MBOX_CMD_FREE_OFFSET 0x14
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#define MBOX_CMD_BUFFER_SIZE 32
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#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
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#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
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#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
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#define MBOX_INDIRECT (1 << 11)
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#define MBOX_INSUFFICIENT_BUFFER -2
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#define MBOX_CIN 0x00
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#define MBOX_ROUT 0x04
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#define MBOX_URG 0x08
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#define MBOX_INT 0x0C
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#define MBOX_COUT 0x20
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#define MBOX_RIN 0x24
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#define MBOX_STATUS 0x2C
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#define MBOX_CMD_BUFFER 0x40
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#define MBOX_RESP_BUFFER 0xC0
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_RESP_OK 0
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#define MBOX_RESP_INVALID_CMD 1
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#define MBOX_RESP_UNKNOWN_BR 2
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#define MBOX_RESP_UNKNOWN 3
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#define MBOX_RESP_NOT_CONFIGURED 256
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/* Mailbox SDM doorbell */
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#define MBOX_DOORBELL_TO_SDM 0x400
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#define MBOX_DOORBELL_FROM_SDM 0x480
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/* Mailbox QSPI commands */
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#define MBOX_CMD_RESTART 2
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#define MBOX_CMD_QSPI_OPEN 50
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#define MBOX_CMD_QSPI_CLOSE 51
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#define MBOX_CMD_QSPI_DIRECT 59
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#define MBOX_CMD_GET_IDCODE 16
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#define MBOX_CMD_QSPI_SET_CS 52
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/* Mailbox REBOOT commands */
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#define MBOX_CMD_REBOOT_HPS 71
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/* Generic error handling */
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#define MBOX_TIMEOUT -2047
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#define MBOX_NO_RESPONSE -2
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#define MBOX_WRONG_ID -3
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/* Mailbox status */
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#define RECONFIG_STATUS_STATE 0
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#define RECONFIG_STATUS_PIN_STATUS 2
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#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
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#define PIN_STATUS_NSTATUS (1U << 31)
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#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
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#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
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#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
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#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
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/* SMC function IDs for SiP Service queries */
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_UID 0x8200ff01
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#define SIP_SVC_VERSION 0x8200ff03
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/* SiP Service Calls version numbers */
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#define SIP_SVC_VERSION_MAJOR 0
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#define SIP_SVC_VERSION_MINOR 1
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/* Mailbox reconfiguration commands */
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#define MBOX_RECONFIG 6
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#define MBOX_RECONFIG_DATA 8
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#define MBOX_RECONFIG_STATUS 9
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/* Sip get memory */
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#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
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#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
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#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
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#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
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#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
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#define INTEL_SIP_SMC_STATUS_OK 0
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#define INTEL_SIP_SMC_STATUS_ERROR 0x4
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#define INTEL_SIP_SMC_STATUS_BUSY 0x1
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#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216
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void mailbox_set_int(int interrupt_input);
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int mailbox_init(void);
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void mailbox_set_qspi_close(void);
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void mailbox_set_qspi_open(void);
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void mailbox_set_qspi_direct(void);
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int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
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int len, int urgent, uint32_t *response);
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void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
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int len, int urgent);
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int mailbox_read_response(int job_id, uint32_t *response);
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int mailbox_get_qspi_clock(void);
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void mailbox_reset_cold(void);
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#endif
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