mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-25 22:35:42 +00:00
b19498b97b
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
422 lines
13 KiB
C
422 lines
13 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* CP110 Marvell SoC driver */
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/marvell/amb_adec.h>
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#include <drivers/marvell/iob.h>
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#include <drivers/marvell/mochi/cp110_setup.h>
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#include <plat_marvell.h>
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/*
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* AXI Configuration.
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*/
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/* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */
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#define MVEBU_AXI_ATTR_OFFSET (0x441300)
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#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \
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0x4 * index)
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/* AXI Protection bits */
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#define MVEBU_AXI_PROT_OFFSET (0x441200)
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/* AXI Protection regs */
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#define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \
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(MVEBU_AXI_PROT_OFFSET + \
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0x4 * index) : \
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(MVEBU_AXI_PROT_OFFSET + 0x18))
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#define MVEBU_AXI_PROT_REGS_NUM (6)
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#define MVEBU_SOC_CFGS_OFFSET (0x441900)
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#define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \
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0x4 * index)
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#define MVEBU_SOC_CFG_REG_NUM (0)
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#define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE)
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/* SATA3 MBUS to AXI regs */
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#define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10)
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#define MVEBU_BRIDGE_WIN_DIS_OFF (0x0)
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/* SATA3 MBUS to AXI regs */
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#define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04)
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/* AXI to MBUS bridge registers */
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#define MVEBU_AMB_IP_OFFSET (0x13ff00)
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#define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \
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(win * 0x8))
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#define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0
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#define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \
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(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
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#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16
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#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \
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(0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
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#define MVEBU_SAMPLE_AT_RESET_REG (0x440600)
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#define SAR_PCIE1_CLK_CFG_OFFSET 31
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#define SAR_PCIE1_CLK_CFG_MASK (0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
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#define SAR_PCIE0_CLK_CFG_OFFSET 30
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#define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
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#define SAR_I2C_INIT_EN_OFFSET 24
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#define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET)
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/*******************************************************************************
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* PCIE clock buffer control
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******************************************************************************/
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#define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0)
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#define PCIE1_REFCLK_BUFF_SOURCE 0x800
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#define PCIE0_REFCLK_BUFF_SOURCE 0x400
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/*******************************************************************************
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* MSS Device Push Set Register
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******************************************************************************/
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#define MVEBU_CP_MSS_DPSHSR_REG (0x280040)
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#define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8
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/*******************************************************************************
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* RTC Configuration
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******************************************************************************/
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#define MVEBU_RTC_BASE (0x284000)
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#define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0)
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#define MVEBU_RTC_STATUS_ALARM1_MASK 0x1
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#define MVEBU_RTC_STATUS_ALARM2_MASK 0x2
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#define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4)
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#define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8)
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#define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC)
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#define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10)
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#define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14)
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#define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18)
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#define MVEBU_RTC_NOMINAL_TIMING 0x2000
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#define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF
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#define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C)
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#define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80)
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#define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF
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#define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF
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#define MVEBU_RTC_WRCLK_SETUP_OFFS 16
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#define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000
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#define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29
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#define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84)
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#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF
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#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F
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enum axi_attr {
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AXI_ADUNIT_ATTR = 0,
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AXI_COMUNIT_ATTR,
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AXI_EIP197_ATTR,
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AXI_USB3D_ATTR,
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AXI_USB3H0_ATTR,
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AXI_USB3H1_ATTR,
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AXI_SATA0_ATTR,
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AXI_SATA1_ATTR,
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AXI_DAP_ATTR,
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AXI_DFX_ATTR,
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AXI_DBG_TRC_ATTR = 12,
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AXI_SDIO_ATTR,
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AXI_MSS_ATTR,
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AXI_MAX_ATTR,
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};
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/* Most stream IDS are configured centrally in the CP-110 RFU
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* but some are configured inside the unit registers
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*/
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#define RFU_STREAM_ID_BASE (0x450000)
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#define USB3H_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0xC)
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#define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10)
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#define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14)
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#define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18)
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#define CP_DMA_0_STREAM_ID_REG (0x6B0010)
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#define CP_DMA_1_STREAM_ID_REG (0x6D0010)
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/* We allocate IDs 128-255 for PCIe */
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#define MAX_STREAM_ID (0x80)
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uintptr_t stream_id_reg[] = {
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USB3H_0_STREAM_ID_REG,
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USB3H_1_STREAM_ID_REG,
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CP_DMA_0_STREAM_ID_REG,
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CP_DMA_1_STREAM_ID_REG,
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SATA_0_STREAM_ID_REG,
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SATA_1_STREAM_ID_REG,
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0
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};
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static void cp110_errata_wa_init(uintptr_t base)
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{
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uint32_t data;
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/* ERRATA GL-4076863:
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* Reset value for global_secure_enable inputs must be changed
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* from '1' to '0'.
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* When asserted, only "secured" transactions can enter IHB
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* configuration space.
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* However, blocking AXI transactions is performed by IOB.
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* Performing it also at IHB/HB complicates programming model.
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*
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* Enable non-secure access in SOC configuration register
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*/
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data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM));
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data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK;
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mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data);
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}
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static void cp110_pcie_clk_cfg(uintptr_t base)
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{
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uint32_t pcie0_clk, pcie1_clk, reg;
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/*
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* Determine the pcie0/1 clock direction (input/output) from the
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* sample at reset.
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*/
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reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG);
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pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET;
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pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET;
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/* CP110 revision A2 */
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if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) {
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/*
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* PCIe Reference Clock Buffer Control register must be
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* set according to the clock direction (input/output)
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*/
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reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL);
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reg &= ~(PCIE0_REFCLK_BUFF_SOURCE | PCIE1_REFCLK_BUFF_SOURCE);
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if (!pcie0_clk)
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reg |= PCIE0_REFCLK_BUFF_SOURCE;
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if (!pcie1_clk)
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reg |= PCIE1_REFCLK_BUFF_SOURCE;
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mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg);
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}
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/* CP110 revision A1 */
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if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) {
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if (!pcie0_clk || !pcie1_clk) {
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/*
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* if one of the pcie clocks is set to input,
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* we need to set mss_push[131] field, otherwise,
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* the pcie clock might not work.
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*/
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reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG);
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reg |= MSS_DPSHSR_REG_PCIE_CLK_SEL;
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mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg);
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}
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}
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}
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/* Set a unique stream id for all DMA capable devices */
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static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id)
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{
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int i = 0;
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while (stream_id_reg[i]) {
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if (i > MAX_STREAM_ID_PER_CP) {
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NOTICE("Only first %d (maximum) Stream IDs allocated\n",
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MAX_STREAM_ID_PER_CP);
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return;
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}
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if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) ||
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(stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG))
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mmio_write_32(base + stream_id_reg[i],
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stream_id << 16 | stream_id);
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else
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mmio_write_32(base + stream_id_reg[i], stream_id);
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/* SATA port 0/1 are in the same SATA unit, and they should use
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* the same STREAM ID number
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*/
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if (stream_id_reg[i] != SATA_0_STREAM_ID_REG)
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stream_id++;
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i++;
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}
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}
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static void cp110_axi_attr_init(uintptr_t base)
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{
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uint32_t index, data;
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/* Initialize AXI attributes for Armada-7K/8K SoC */
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/* Go over the AXI attributes and set Ax-Cache and Ax-Domain */
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for (index = 0; index < AXI_MAX_ATTR; index++) {
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switch (index) {
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/* DFX and MSS unit works with no coherent only -
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* there's no option to configure the Ax-Cache and Ax-Domain
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*/
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case AXI_DFX_ATTR:
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case AXI_MSS_ATTR:
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continue;
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default:
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/* Set Ax-Cache as cacheable, no allocate, modifiable,
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* bufferable
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* The values are different because Read & Write
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* definition is different in Ax-Cache
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*/
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data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index));
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data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK;
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data |= (CACHE_ATTR_WRITE_ALLOC |
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CACHE_ATTR_CACHEABLE |
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CACHE_ATTR_BUFFERABLE) <<
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MVEBU_AXI_ATTR_ARCACHE_OFFSET;
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data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK;
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data |= (CACHE_ATTR_READ_ALLOC |
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CACHE_ATTR_CACHEABLE |
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CACHE_ATTR_BUFFERABLE) <<
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MVEBU_AXI_ATTR_AWCACHE_OFFSET;
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/* Set Ax-Domain as Outer domain */
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data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK;
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data |= DOMAIN_OUTER_SHAREABLE <<
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MVEBU_AXI_ATTR_ARDOMAIN_OFFSET;
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data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK;
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data |= DOMAIN_OUTER_SHAREABLE <<
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MVEBU_AXI_ATTR_AWDOMAIN_OFFSET;
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mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data);
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}
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}
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/* SATA IOCC supported, cache attributes
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* for SATA MBUS to AXI configuration.
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*/
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data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG);
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data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK;
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data |= (CACHE_ATTR_WRITE_ALLOC |
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CACHE_ATTR_CACHEABLE |
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CACHE_ATTR_BUFFERABLE) <<
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MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET;
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data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK;
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data |= (CACHE_ATTR_READ_ALLOC |
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CACHE_ATTR_CACHEABLE |
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CACHE_ATTR_BUFFERABLE) <<
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MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET;
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mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data);
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/* Set all IO's AXI attribute to non-secure access. */
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for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++)
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mmio_write_32(base + MVEBU_AXI_PROT_REG(index),
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DOMAIN_SYSTEM_SHAREABLE);
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}
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static void amb_bridge_init(uintptr_t base)
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{
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uint32_t reg;
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/* Open AMB bridge Window to Access COMPHY/MDIO registers */
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reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0));
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reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK |
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MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK);
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reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) |
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(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET);
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mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg);
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}
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static void cp110_rtc_init(uintptr_t base)
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{
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/* Update MBus timing parameters before accessing RTC registers */
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mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
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MVEBU_RTC_WRCLK_PERIOD_MASK,
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MVEBU_RTC_WRCLK_PERIOD_DEFAULT);
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mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
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MVEBU_RTC_WRCLK_SETUP_MASK,
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MVEBU_RTC_WRCLK_SETUP_DEFAULT <<
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MVEBU_RTC_WRCLK_SETUP_OFFS);
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mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG,
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MVEBU_RTC_READ_OUTPUT_DELAY_MASK,
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MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT);
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/*
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* Issue reset to the RTC if Clock Correction register
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* contents did not sustain the reboot/power-on.
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*/
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if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) &
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MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) {
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/* Reset Test register */
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mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0);
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mdelay(500);
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/* Reset Status register */
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mmio_write_32(base + MVEBU_RTC_STATUS_REG,
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(MVEBU_RTC_STATUS_ALARM1_MASK |
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MVEBU_RTC_STATUS_ALARM2_MASK));
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udelay(62);
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/* Turn off Int1 and Int2 sources & clear the Alarm count */
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mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0);
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mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0);
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mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0);
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mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0);
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/* Setup nominal register access timing */
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mmio_write_32(base + MVEBU_RTC_CCR_REG,
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MVEBU_RTC_NOMINAL_TIMING);
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/* Reset Status register */
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mmio_write_32(base + MVEBU_RTC_STATUS_REG,
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(MVEBU_RTC_STATUS_ALARM1_MASK |
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MVEBU_RTC_STATUS_ALARM2_MASK));
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udelay(50);
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}
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}
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static void cp110_amb_adec_init(uintptr_t base)
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{
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/* enable AXI-MBUS by clearing "Bridge Windows Disable" */
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mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG,
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(1 << MVEBU_BRIDGE_WIN_DIS_OFF));
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/* configure AXI-MBUS windows for CP */
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init_amb_adec(base);
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}
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void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
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{
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INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
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/* configure IOB windows for CP0*/
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init_iob(cp110_base);
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/* configure AXI-MBUS windows for CP0*/
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cp110_amb_adec_init(cp110_base);
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/* configure axi for CP0*/
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cp110_axi_attr_init(cp110_base);
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/* Execute SW WA for erratas */
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cp110_errata_wa_init(cp110_base);
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/* Confiure pcie clock according to clock direction */
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cp110_pcie_clk_cfg(cp110_base);
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/* configure stream id for CP0 */
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cp110_stream_id_init(cp110_base, stream_id);
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/* Open AMB bridge for comphy for CP0 & CP1*/
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amb_bridge_init(cp110_base);
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/* Reset RTC if needed */
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cp110_rtc_init(cp110_base);
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}
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/* Do the minimal setup required to configure the CP in BLE */
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void cp110_ble_init(uintptr_t cp110_base)
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{
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#if PCI_EP_SUPPORT
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INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
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amb_bridge_init(cp110_base);
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/* Configure PCIe clock */
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cp110_pcie_clk_cfg(cp110_base);
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/* Configure PCIe endpoint */
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ble_plat_pcie_ep_setup();
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#endif
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}
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