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https://github.com/ARM-software/arm-trusted-firmware.git
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cfe19f85c9
Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <common_def.h>
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/* CPU topology */
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#define PLAT_MAX_CORES_PER_CLUSTER 2
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#define PLAT_CLUSTER_COUNT 12
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#define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \
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PLAT_MAX_CORES_PER_CLUSTER)
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 4
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#define MAX_MMAP_REGIONS 6
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#define PLATFORM_STACK_SIZE 0x400
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#define BL31_BASE 0x04000000
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#define BL31_SIZE 0x00080000
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#define PLAT_SQ_CCN_BASE 0x32000000
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#define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \
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0, /* Cluster 0 */ \
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18, /* Cluster 1 */ \
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11, /* Cluster 2 */ \
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29, /* Cluster 3 */ \
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35, /* Cluster 4 */ \
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17, /* Cluster 5 */ \
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12, /* Cluster 6 */ \
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30, /* Cluster 7 */ \
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14, /* Cluster 8 */ \
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32, /* Cluster 9 */ \
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15, /* Cluster 10 */ \
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33 /* Cluster 11 */
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/* UART related constants */
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#define PLAT_SQ_BOOT_UART_BASE 0x2A400000
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#define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000
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#define SQ_CONSOLE_BAUDRATE 115200
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#define SQ_SYS_CNTCTL_BASE 0x2a430000
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#define SQ_SYS_TIMCTL_BASE 0x2a810000
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#define PLAT_SQ_NSTIMER_FRAME_ID 0
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#define DRAMINFO_BASE 0x2E00FFC0
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#define PLAT_SQ_MHU_BASE 0x45000000
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#define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000
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#define SCPI_CMD_GET_DRAMINFO 0x1
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#define SQ_BOOT_CFG_ADDR 0x45410000
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#define PLAT_SQ_PRIMARY_CPU_SHIFT 8
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#define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6
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#define PLAT_SQ_GICD_BASE 0x30000000
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#define PLAT_SQ_GICR_BASE 0x30400000
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#endif /* __PLATFORM_DEF_H__ */
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