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e8e87683f2
During suspend, it is necessary to set some power rails of the PMIC to enter low power mode to achieve power saving. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Change-Id: Iaeadd15270e0209f027fab80f478ad621bd59ea7
255 lines
6.4 KiB
C
255 lines
6.4 KiB
C
/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <drivers/pmic/pmic_set_lowpower.h>
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#include <drivers/spmi/spmi_common.h>
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#include <lib/mtk_init/mtk_init.h>
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#include <mt_spm_constraint.h>
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#include <mt_spm_pmic_lp.h>
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#include <mt_spm_reg.h>
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/* SPMI_M: 6363, SPMI_P: 6373/6316 */
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/* SPMI_M: 6363, SPMI_P: 6373/6316 */
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static struct lp_pmic_cfg {
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uint8_t slave;
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uint8_t master;
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char *name;
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} pmics[] = {
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[LP_MT6363] = {MT6363_SLAVE, SPMI_MASTER_1, "MT6363"},
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[LP_MT6373] = {MT6373_SLAVE, SPMI_MASTER_P_1, "MT6373"},
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[LP_MT6316_1] = {MT6316_S8_SLAVE, SPMI_MASTER_P_1, "MT6316_S8"},
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[LP_MT6316_2] = {MT6316_S6_SLAVE, SPMI_MASTER_P_1, "MT6316_S6"},
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[LP_MT6316_3] = {MT6316_S7_SLAVE, SPMI_MASTER_P_1, "MT6316_S7"},
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[LP_MT6316_4] = {MT6316_S15_SLAVE, SPMI_MASTER_P_1, "MT6316_S15"},
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};
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#ifdef MTK_SPM_PMIC_GS_DUMP
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static struct pmic_gs_info pmic_gs_dump_info;
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static char *pmic_str[] = {
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[LP_MT6363] = "MT6363",
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[LP_MT6373] = "MT6373",
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[LP_MT6316_1] = "MT6316_1",
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[LP_MT6316_2] = "MT6316_2",
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[LP_MT6316_3] = "MT6316_3",
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[LP_MT6316_4] = "MT6316_4",
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};
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#endif
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struct spmi_device *lp_sdev[LP_PMIC_SLAVE_NUM];
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#define VSRAM_CORE_0_35V 56
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#define VSRAM_CORE_0_55V 88
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#define VSRAM_CORE_0_75V 120
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/* VSRAM_CORE Low bound */
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#ifdef MTK_AGING_FLAVOR_LOAD
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#define SUSPEND_AGING_VAL_SHIFT 3
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#define SUSPEND_AGING_VAL_DEFAULT 85
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#define VSRAM_CORE_LOWBOUND (74 - SUSPEND_AGING_VAL_SHIFT)
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#else
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#define VSRAM_CORE_LOWBOUND 74
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#endif
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#define MT6363_LP_REG 0x1687
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#define MT6363_VIO18_SWITCH 0x53
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#define MT6373_VIO18_SWITCH 0x58
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static uint32_t vcore_sram_suspend_vol = VSRAM_CORE_0_55V;
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static bool vcore_sram_lp_enable = true;
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static bool vcore_lp_enable = true;
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static uint32_t get_vcore_sram_suspend_vol(void)
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{
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uint8_t value;
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/* Set vcore_sram to 0.55V by default */
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value = VSRAM_CORE_0_55V;
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#ifdef MTK_AGING_FLAVOR_LOAD
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value -= SUSPEND_AGING_VAL_SHIFT;
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if (value > SUSPEND_AGING_VAL_DEFAULT)
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value = SUSPEND_AGING_VAL_DEFAULT;
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INFO("%s(%d) enable aging with value: %u\n",
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__func__, __LINE__, value);
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#endif
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return value;
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}
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#ifdef MTK_SPM_PMIC_GS_DUMP
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static void mt_spm_dump_pmic_gs(uint32_t cmd)
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{
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#ifdef MTK_SPM_PMIC_GS_DUMP_SUSPEND
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if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) { /* Suspend enter */
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mt_spm_pmic_gs_dump(SUSPEND, LP_MT6363);
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mt_spm_pmic_gs_dump(SUSPEND, LP_MT6373);
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}
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#endif
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if (cmd & MT_RM_CONSTRAINT_ALLOW_VCORE_LP) {
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if (cmd & MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF) { /* SODI3 */
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#ifdef MTK_SPM_PMIC_GS_DUMP_SODI3
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mt_spm_pmic_gs_dump(SODI3, LP_MT6363);
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mt_spm_pmic_gs_dump(SODI3, LP_MT6373);
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#endif
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} else { /* DPIDLE enter */
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#ifdef MTK_SPM_PMIC_GS_DUMP_DPIDLE
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mt_spm_pmic_gs_dump(DPIDLE, LP_MT6363);
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mt_spm_pmic_gs_dump(DPIDLE, LP_MT6373);
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#endif
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}
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}
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}
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#endif
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int spm_lp_setting_init(void)
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{
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uint8_t i, slvid, spmi_master;
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for (i = 0; i < ARRAY_SIZE(pmics); i++) {
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slvid = pmics[i].slave;
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spmi_master = pmics[i].master;
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lp_sdev[i] = get_spmi_device(spmi_master, slvid);
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if (!lp_sdev[i])
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return -ENODEV;
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}
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PMIC_SLVID_BUCK_SET_LP(MT6316, S8, VBUCK1, RC8,
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false, OP_MODE_LP, HW_OFF);
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/* Get suspend case vcore_sram sleep voltage */
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vcore_sram_suspend_vol = get_vcore_sram_suspend_vol();
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#ifdef MTK_SPM_PMIC_GS_DUMP
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pmic_gs_dump_info.lp_sdev = lp_sdev;
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pmic_gs_dump_info.pmic_str = pmic_str;
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pmic_gs_dump_info.pmic_num = LP_PMIC_SLAVE_NUM;
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#ifdef MTK_SPM_PMIC_GS_DUMP_SUSPEND
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pmic_gs_dump_info.scen_gs[SUSPEND].data = pmic_gs_suspend;
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#endif
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#ifdef MTK_SPM_PMIC_GS_DUMP_SODI3
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pmic_gs_dump_info.scen_gs[SODI3].data = pmic_gs_sodi3;
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#endif
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#ifdef MTK_SPM_PMIC_GS_DUMP_DPIDLE
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pmic_gs_dump_info.scen_gs[DPIDLE].data = pmic_gs_dpidle;
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#endif
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return register_pmic_gs_info(&pmic_gs_dump_info);
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#else
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return 0;
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#endif
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}
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#ifdef MTK_SPM_PMIC_LP_SUPPORT
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MTK_PLAT_SETUP_0_INIT(spm_lp_setting_init);
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#endif
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void set_vcore_lp_enable(bool enable)
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{
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vcore_lp_enable = enable;
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}
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bool get_vcore_lp_enable(void)
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{
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return vcore_lp_enable;
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}
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void set_vsram_lp_enable(bool enable)
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{
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vcore_sram_lp_enable = enable;
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}
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bool get_vsram_lp_enable(void)
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{
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return vcore_sram_lp_enable;
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}
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void set_vsram_lp_volt(uint32_t volt)
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{
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/* Allow 0.35V ~ 0.75V */
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if (volt < VSRAM_CORE_0_35V || volt > VSRAM_CORE_0_75V)
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return;
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vcore_sram_suspend_vol = volt;
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}
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uint32_t get_vsram_lp_volt(void)
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{
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return vcore_sram_suspend_vol;
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}
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static int pmic_lp_setting(uint8_t data)
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{
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int ret;
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if (data != 0x0 && data != 0x1)
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return -ENODEV;
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/* SUSPEND:VS1 HW2&RC9 normal mode */
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PMIC_BUCK_SET_LP(MT6363, VS1, HW2,
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false, OP_MODE_LP, HW_LP);
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PMIC_BUCK_SET_LP(MT6363, VS1, RC9,
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false, OP_MODE_MU, HW_ON);
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PMIC_LDO_SET_LP(MT6363, VIO18, HW2,
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false, OP_MODE_LP, HW_LP);
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PMIC_LDO_SET_LP(MT6363, VIO18, RC9,
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false, OP_MODE_MU, HW_ON);
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/* Switch DIG18 to VIO18 for power saving */
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ret = spmi_ext_register_writel(lp_sdev[LP_MT6363], MT6363_VIO18_SWITCH, &data, 1);
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if (ret)
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INFO("MT6363 RG_VIO18 spmi failed\n");
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ret = spmi_ext_register_writel(lp_sdev[LP_MT6373], MT6373_VIO18_SWITCH, &data, 1);
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if (ret)
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INFO("MT6373 RG_VIO18 spmi failed\n");
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return ret;
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}
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int do_spm_low_power(enum SPM_PWR_TYPE type, uint32_t cmd)
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{
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int ret;
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uint8_t value;
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bool enter_suspend, vcore_sram_lp = false;
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if (type == SPM_LP_ENTER) {
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enter_suspend = true;
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vcore_sram_lp = vcore_sram_lp_enable;
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if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND) {
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value = vcore_sram_suspend_vol;
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if (value < VSRAM_CORE_LOWBOUND ||
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value > VSRAM_CORE_0_75V) {
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INFO("Vsram_core voltage wrong\n");
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panic();
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}
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} else {
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value = VSRAM_CORE_0_55V;
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}
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} else {
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enter_suspend = false;
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vcore_sram_lp = false;
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value = VSRAM_CORE_0_75V;
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}
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/* Enable VA12_2/VSRAM_CPUL HW_LP for suspend/idle */
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PMIC_LDO_SET_LP(MT6363, VA12_2, HW2, enter_suspend, OP_MODE_LP, HW_LP);
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PMIC_LDO_SET_LP(MT6363, VSRAM_CPUL, HW2,
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enter_suspend, OP_MODE_LP, HW_LP);
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if (!(cmd & MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND))
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return 0;
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PMIC_SLVID_BUCK_SET_LP(MT6316, S8, VBUCK1, HW2, vcore_lp_enable,
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OP_MODE_LP, HW_LP);
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PMIC_BUCK_SET_LP(MT6363, VBUCK4, HW0, vcore_sram_lp,
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OP_MODE_LP, HW_LP);
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PMIC_BUCK_SET_LP(MT6363, VBUCK4, HW2, !enter_suspend,
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OP_MODE_LP, HW_LP);
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ret = spmi_ext_register_writel(lp_sdev[LP_MT6363], MT6363_LP_REG, &value, 1);
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if (ret)
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INFO("BUCK(VSRAM_CORE) spmi write failed\n");
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if (cmd & MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND)
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pmic_lp_setting(enter_suspend ? 1 : 0);
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return 0;
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}
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