mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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a24b53e0e5
This patch mainly initializes the SPM and provides common APIs for SPM to enable the use of its various features. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Change-Id: I9facb6bf9962bb2d5fcacd945846bfaeb4c87a55
464 lines
9.6 KiB
C
464 lines
9.6 KiB
C
/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stddef.h>
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#include <stdio.h>
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#include <string.h>
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#include <arch.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <drivers/gpio.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <platform_def.h>
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#include <constraints/mt_spm_rc_api.h>
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#include <constraints/mt_spm_rc_internal.h>
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#include <drivers/spm/mt_spm_resource_req.h>
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#include <lib/mtk_init/mtk_init.h>
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#include <lib/pm/mtk_pm.h>
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#include <lpm_v2/mt_lp_rm.h>
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#include <lpm_v2/mt_lp_rqm.h>
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#include <lpm_v2/mt_lpm_smc.h>
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#include <mt_plat_spm_setting.h>
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#include <mt_spm.h>
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#include <mt_spm_common.h>
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#include <mt_spm_conservation.h>
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#include <mt_spm_constraint.h>
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#include <mt_spm_dispatcher.h>
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#include <mt_spm_hwreq.h>
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#include <mt_spm_idle.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_reg.h>
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#include <mt_spm_suspend.h>
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#include <mtk_mmap_pool.h>
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#include <sleep_def.h>
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#ifdef MT_SPM_USING_BAKERY_LOCK
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DEFINE_BAKERY_LOCK(spm_lock);
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#define plat_spm_lock_init() \
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bakery_lock_init(&spm_lock)
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#else
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spinlock_t spm_lock;
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#define plat_spm_lock_init()
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#endif
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uint32_t mt_spm_version;
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static uint32_t spm_irq_num;
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void spm_set_sysclk_settle(void)
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{
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uint32_t settle;
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mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE);
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settle = mmio_read_32(SPM_CLK_SETTLE);
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INFO("md_settle = %u, settle = %u\n", SPM_SYSCLK_SETTLE, settle);
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}
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void spm_set_irq_num(uint32_t num)
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{
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spm_irq_num = num;
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}
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void spm_irq0_handler(uint64_t x1, uint64_t x2)
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{
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if (x2 == 0) {
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mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
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mmio_write_32(SPM_IRQ_STA, x1);
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mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT0);
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}
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}
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static int spm_ap_mdsrc_ack(void)
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{
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int ack, md_state = 0;
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/* Check ap_mdsrc_ack = 1'b1, for md internal resource on ack */
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ack = !!(mmio_read_32(AP_MDSRC_REQ) & AP_MDSMSRC_ACK_LSB);
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if (!ack) {
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/* Check md_apsrc_req = 1'b0, for md state 0:sleep, 1:wakeup */
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md_state = !!(mmio_read_32(SPM_REQ_STA_10)
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& MD_APSRC_REQ_LSB);
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ERROR("[SPM] error: md_sleep = %d\n", md_state);
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ERROR("%s can not get AP_MDSRC_ACK\n", __func__);
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return -1;
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}
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return 0;
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}
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static void spm_ap_mdsrc_req(int set)
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{
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spm_lock_get();
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if (set)
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mmio_setbits_32(AP_MDSRC_REQ, AP_MDSMSRC_REQ_LSB);
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else
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mmio_clrbits_32(AP_MDSRC_REQ, AP_MDSMSRC_REQ_LSB);
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spm_lock_release();
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}
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static int spm_is_md_sleep(void *priv)
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{
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int md_state = 0;
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int *sleep = (int *)priv;
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if (!priv)
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return -1;
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/* Check md_apsrc_req = 1'b0, for md state 0:sleep, 1:wakeup */
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md_state = !!(mmio_read_32(SPM_REQ_STA_10)
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& MD_APSRC_REQ_LSB);
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if (md_state == 0)
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*sleep = 1;
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else
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*sleep = 0;
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return 0;
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}
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static void spm_ap_gpueb_pll_control(int set)
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{
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spm_lock_get();
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if (set)
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mmio_setbits_32(SPM2GPUPM_CON, SC_MFG_PLL_EN_LSB);
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else
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mmio_clrbits_32(SPM2GPUPM_CON, SC_MFG_PLL_EN_LSB);
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spm_lock_release();
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}
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static uint32_t spm_ap_gpueb_get_pwr_status(void)
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{
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uint32_t ret;
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ret = mmio_read_32(XPU_PWR_STATUS);
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return ret;
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}
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static uint32_t spm_ap_gpueb_get_mfg0_pwr_con(void)
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{
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uint32_t ret;
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ret = mmio_read_32(MFG0_PWR_CON);
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return ret;
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}
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#ifndef MTK_PLAT_SPM_UNSUPPORT
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struct mt_lp_res_req rq_xo_fpm = {
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.res_id = MT_LP_RQ_XO_FPM,
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.res_rq = MT_SPM_XO_FPM,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_26m = {
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.res_id = MT_LP_RQ_26M,
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.res_rq = MT_SPM_26M,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_infra = {
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.res_id = MT_LP_RQ_INFRA,
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.res_rq = MT_SPM_INFRA,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_syspll = {
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.res_id = MT_LP_RQ_SYSPLL,
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.res_rq = MT_SPM_SYSPLL,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_dram_s0 = {
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.res_id = MT_LP_RQ_DRAM,
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.res_rq = MT_SPM_DRAM_S0,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_dram_s1 = {
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.res_id = MT_LP_RQ_DRAM,
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.res_rq = MT_SPM_DRAM_S1,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_vcore = {
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.res_id = MT_LP_RQ_VCORE,
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.res_rq = MT_SPM_VCORE,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_emi = {
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.res_id = MT_LP_RQ_EMI,
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.res_rq = MT_SPM_EMI,
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.res_usage = 0,
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};
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struct mt_lp_res_req rq_pmic = {
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.res_id = MT_LP_RQ_PMIC,
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.res_rq = MT_SPM_PMIC,
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.res_usage = 0,
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};
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struct mt_lp_res_req *spm_resources[] = {
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&rq_xo_fpm,
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&rq_26m,
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&rq_infra,
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&rq_syspll,
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&rq_dram_s0,
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&rq_dram_s1,
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&rq_vcore,
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&rq_emi,
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&rq_pmic,
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NULL,
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};
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struct mt_resource_req_manager plat_mt8196_rq = {
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.res = spm_resources,
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};
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struct mt_resource_constraint plat_constraint_vcore = {
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.is_valid = spm_is_valid_rc_vcore,
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.update = spm_update_rc_vcore,
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.allow = spm_allow_rc_vcore,
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.run = spm_run_rc_vcore,
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.reset = spm_reset_rc_vcore,
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.get_status = spm_get_status_rc_vcore,
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};
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struct mt_resource_constraint plat_constraint_bus26m = {
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.is_valid = spm_is_valid_rc_bus26m,
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.update = spm_update_rc_bus26m,
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.allow = spm_allow_rc_bus26m,
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.run = spm_run_rc_bus26m,
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.reset = spm_reset_rc_bus26m,
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.get_status = spm_get_status_rc_bus26m,
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};
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struct mt_resource_constraint plat_constraint_syspll = {
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.is_valid = spm_is_valid_rc_syspll,
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.update = spm_update_rc_syspll,
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.allow = spm_allow_rc_syspll,
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.run = spm_run_rc_syspll,
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.reset = spm_reset_rc_syspll,
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.get_status = spm_get_status_rc_syspll,
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};
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struct mt_resource_constraint *plat_constraints[] = {
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&plat_constraint_vcore,
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&plat_constraint_bus26m,
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&plat_constraint_syspll,
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NULL,
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};
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#endif
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int mt_spm_hwctrl(uint32_t type, int set, void *priv)
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{
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int ret = 0;
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if (type == PLAT_AP_MDSRC_REQ) {
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spm_ap_mdsrc_req(set);
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} else if (type == PLAT_AP_MDSRC_ACK) {
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ret = spm_ap_mdsrc_ack();
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} else if (type == PLAT_AP_IS_MD_SLEEP) {
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ret = spm_is_md_sleep(priv);
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} else if (type == PLAT_AP_MDSRC_SETTLE) {
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if (!priv)
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return -1;
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*(int *)priv = AP_MDSRC_REQ_MD_26M_SETTLE;
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} else if (type == PLAT_AP_GPUEB_PLL_CONTROL) {
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spm_ap_gpueb_pll_control(set);
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} else if (type == PLAT_AP_GPUEB_PWR_STATUS) {
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if (!priv)
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return -1;
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*(uint32_t *)priv = spm_ap_gpueb_get_pwr_status();
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} else if (type == PLAT_AP_GPUEB_MFG0_PWR_CON) {
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if (!priv)
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return -1;
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*(uint32_t *)priv = spm_ap_gpueb_get_mfg0_pwr_con();
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} else if (type == PLAT_AP_SPM_RESOURCE_REQUEST_UPDATE) {
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struct spm_lp_scen *spmlp = NULL;
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#ifdef MT_SPM_COMMON_SODI_SUPPORT
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mt_spm_common_sodi_get_spm_lp(&spmlp);
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#else
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#if defined(MT_SPM_FEATURE_SUPPORT)
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mt_spm_idle_generic_get_spm_lp(&spmlp);
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#endif
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#endif
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if (!spmlp)
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return -1;
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__spm_set_power_control(spmlp->pwrctrl, *(uint32_t *)priv);
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ret = __spm_wait_spm_request_ack(*(uint32_t *)priv,
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SPM_ACK_TIMEOUT_US);
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} else if (type == PLAT_AP_SPM_WDT_TRIGGER) {
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mmio_write_32(PCM_WDT_VAL, 0x1);
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mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY |
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REG_PCM_WDT_EN_LSB | REG_PCM_WDT_WAKE_LSB);
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} else {
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/* Not supported type */
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return -1;
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}
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return ret;
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}
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#ifndef MTK_PLAT_SPM_UNSUPPORT
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struct mt_resource_manager plat_mt8196_rm = {
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.update = NULL,
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.hwctrl = mt_spm_hwctrl,
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.consts = plat_constraints,
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};
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#else
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struct mt_resource_manager plat_mt8196_rm = {
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.hwctrl = mt_spm_hwctrl,
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};
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#endif
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/* Determine for spm sw resource user */
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static struct mt_lp_resource_user spm_res_user;
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struct mt_lp_resource_user *get_spm_res_user(void)
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{
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return &spm_res_user;
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}
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#ifdef MT_SPM_COMMON_SODI_SUPPORT
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int mt_spm_common_sodi_get_spm_pcm_flag(uint32_t *lp, uint32_t idx)
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{
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struct spm_lp_scen *spmlp;
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struct pwr_ctrl *pwrctrl;
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mt_spm_common_sodi_get_spm_lp(&spmlp);
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pwrctrl = spmlp->pwrctrl;
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if (!lp || idx > 1)
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return -1;
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switch (idx) {
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case 0:
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*lp = pwrctrl->pcm_flags;
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break;
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case 1:
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*lp = pwrctrl->pcm_flags;
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break;
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default:
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return -1;
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}
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return 0;
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}
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void mt_spm_common_sodi_en(bool en)
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{
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struct spm_lp_scen *spmlp;
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struct pwr_ctrl *pwrctrl;
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mt_spm_common_sodi_get_spm_lp(&spmlp);
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pwrctrl = spmlp->pwrctrl;
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#if defined(CONFIG_MTK_VCOREDVFS_SUPPORT)
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__spm_sync_vcore_dvfs_pcm_flags(&pwrctrl->pcm_flags,
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&__spm_vcorefs.pwrctrl->pcm_flags);
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#endif
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if (en)
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pwrctrl->pcm_flags |= SPM_FLAG_ENABLE_COMMON_SODI5;
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else
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pwrctrl->pcm_flags &= (~SPM_FLAG_ENABLE_COMMON_SODI5);
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/* Set PCM flags */
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__spm_set_pcm_flags(pwrctrl);
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__spm_send_cpu_wakeup_event();
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}
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int mt_spm_common_sodi_get_spm_lp(struct spm_lp_scen **lp)
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{
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if (!lp)
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return -1;
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*lp = &__spm_common_sodi;
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return 0;
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}
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void mt_spm_set_common_sodi_pwrctr(void)
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{
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struct resource_req_status common_sodi_spm_resource_req = {
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.id = MT_LP_RQ_ID_ALL_USAGE,
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.val = 0,
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};
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struct spm_lp_scen *spmlp;
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mt_lp_rq_get_status(PLAT_RQ_REQ_USAGE,
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&common_sodi_spm_resource_req);
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mt_spm_common_sodi_get_spm_lp(&spmlp);
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__spm_set_power_control(spmlp->pwrctrl,
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common_sodi_spm_resource_req.val);
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}
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void mt_spm_set_common_sodi_pcm_flags(void)
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{
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struct spm_lp_scen *spmlp;
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struct pwr_ctrl *pwrctrl;
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mt_spm_common_sodi_get_spm_lp(&spmlp);
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pwrctrl = spmlp->pwrctrl;
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#if defined(CONFIG_MTK_VCOREDVFS_SUPPORT)
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/* Set PCM flags */
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__spm_sync_vcore_dvfs_pcm_flags(&pwrctrl->pcm_flags,
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&__spm_vcorefs.pwrctrl->pcm_flags);
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#endif
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__spm_set_pcm_flags(pwrctrl);
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__spm_send_cpu_wakeup_event();
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}
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#endif
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static void spm_gpio_init(void)
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{
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gpio_set_direction(EC_SUSPEND_PIN, GPIO_DIR_OUT);
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gpio_set_value(EC_SUSPEND_PIN, GPIO_LEVEL_HIGH);
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}
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int spm_boot_init(void)
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{
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plat_spm_lock_init();
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#if defined(MT_SPM_FEATURE_SUPPORT)
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plat_spm_pmic_wrap_init();
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#endif
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mt_lp_rm_register(&plat_mt8196_rm);
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#ifndef MTK_PLAT_SPM_UNSUPPORT
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mt_lp_resource_request_manager_register(&plat_mt8196_rq);
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mt_lp_resource_user_register("SPM", &spm_res_user);
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mt_spm_dispatcher_init();
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#endif
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#if defined(MT_SPM_FEATURE_SUPPORT)
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spm_hwreq_init();
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#endif
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spm_gpio_init();
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spm_irq_num = 0xFFFFFFFF;
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INFO("[%s:%d] - spm finished, version = %u, PC = 0x%x\n",
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__func__, __LINE__,
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mt_spm_version, mmio_read_32(MD32PCM_PC));
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return 0;
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}
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MTK_PLAT_SETUP_1_INIT(spm_boot_init);
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