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https://github.com/ARM-software/arm-trusted-firmware.git
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da54c72436
Add topology module to support CPU power state control. Signed-off-by: Kai Liang <kai.liang@mediatek.com> Change-Id: I0cc1e5a426762b1b29bff1e940e077643da02e5e
125 lines
2.9 KiB
C
125 lines
2.9 KiB
C
/*
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* Copyright (c) 2025, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <lib/spinlock.h>
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#include <platform_def.h>
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#include "../inc/pwr_topology.h"
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#include <lib/pm/mtk_pm.h>
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#include <lpm/mt_lp_rm.h>
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#ifdef MT_CPU_PM_USING_BAKERY_LOCK
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DEFINE_BAKERY_LOCK(mt_pwr_lock);
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#define plat_pwr_lock_init() bakery_lock_init(&mt_pwr_lock)
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#define plat_pwr_lock() bakery_lock_get(&mt_pwr_lock)
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#define plat_pwr_unlock() bakery_lock_release(&mt_pwr_lock)
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#else
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spinlock_t mt_pwr_lock;
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#define plat_pwr_lock_init()
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#define plat_pwr_lock() spin_lock(&mt_pwr_lock)
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#define plat_pwr_unlock() spin_unlock(&mt_pwr_lock)
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#endif
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enum mt_pwr_domain_node {
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MT_PWR_NONMCUSYS = 0,
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MT_PWR_MCUSYS_PDN,
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MT_PWR_MAX
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};
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#if CONFIG_MTK_PM_SUPPORT && CONFIG_MTK_CPU_SUSPEND_EN && \
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!CPU_PM_DOMAIN_CORE_ONLY
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static int mt_pwr_domain_st[MT_PWR_MAX];
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#endif
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#define ALL_IN_ONE_GROUP 0xFF
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unsigned int pwr_domain_coordination(enum pwr_domain_status pwr,
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const mtk_pstate_type psci_state,
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const struct mtk_cpupm_pwrstate *state,
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afflv_prepare fn)
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{
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unsigned int pstate = 0;
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#if CONFIG_MTK_PM_SUPPORT && CONFIG_MTK_CPU_SUSPEND_EN && \
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!CPU_PM_DOMAIN_CORE_ONLY
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unsigned int is_flush = 0;
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struct pwr_toplogy tp = {
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.cur_group_bit = ALL_IN_ONE_GROUP,
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.group = ALL_IN_ONE_GROUP,
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};
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/* Skip to process smp */
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if (pwr > PWR_DOMAIN_OFF)
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return pstate;
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if (!IS_MT_PLAT_PWR_STATE_MCUSYS(state->pwr.state_id)) {
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plat_pwr_lock();
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if (pwr == PWR_DOMAIN_OFF)
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mt_pwr_domain_st[MT_PWR_NONMCUSYS] += 1;
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else
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mt_pwr_domain_st[MT_PWR_NONMCUSYS] -= 1;
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flush_dcache_range(
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(uintptr_t)&mt_pwr_domain_st[MT_PWR_NONMCUSYS],
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sizeof(mt_pwr_domain_st[MT_PWR_NONMCUSYS]));
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plat_pwr_unlock();
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}
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plat_pwr_lock();
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if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER)
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pstate |= MT_CPUPM_PWR_DOMAIN_CLUSTER;
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if (psci_get_pstate_pwrlvl(psci_state) >= PLAT_MT_CPU_SUSPEND_CLUSTER)
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pstate |= MT_CPUPM_PWR_DOMAIN_PERCORE_DSU;
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if (pwr == PWR_DOMAIN_OFF) {
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if (IS_PLAT_MCUSYSOFF_AFFLV(state->pwr.afflv) &&
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(mt_pwr_domain_st[MT_PWR_NONMCUSYS] == 0)) {
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int ret = MTK_CPUPM_E_OK;
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tp.group = ALL_IN_ONE_GROUP;
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if (fn)
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ret = fn(1, state, &tp);
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if (ret == MTK_CPUPM_E_OK) {
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pstate |= MT_CPUPM_PWR_DOMAIN_MCUSYS;
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mt_pwr_domain_st[MT_PWR_MCUSYS_PDN] += 1;
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is_flush = 1;
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}
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}
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} else {
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if (mt_pwr_domain_st[MT_PWR_MCUSYS_PDN]) {
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tp.group = 0x0;
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if (fn)
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fn(1, state, &tp);
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pstate |= MT_CPUPM_PWR_DOMAIN_MCUSYS;
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mt_pwr_domain_st[MT_PWR_MCUSYS_PDN] -= 1;
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is_flush = 1;
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}
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if (mt_pwr_domain_st[MT_PWR_NONMCUSYS] < 0)
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assert(0);
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}
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if (is_flush)
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flush_dcache_range(
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(uintptr_t)&mt_pwr_domain_st[MT_PWR_MCUSYS_PDN],
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sizeof(mt_pwr_domain_st[MT_PWR_MCUSYS_PDN]));
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plat_pwr_unlock();
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#endif
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return pstate;
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}
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void pwr_topology_init(void)
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{
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plat_pwr_lock_init();
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}
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