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https://github.com/ARM-software/arm-trusted-firmware.git
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51b8b9c3c4
Add virtio-net and virtio-9p devices to the devicetree without the status set. This ensures that the MMIO frame is set, and it is not fatal to start the driver initialisation procedure, which will typically bail out if it finds zero virtqueues. Add the virtio-rng device with status disabled. The disabled status is chosen because the FVP models have only supported this since 2022 and older models would trigger an external abort when trying to access or probe this MMIO region. This is included by the fvp-base devicetrees. Change-Id: Ia0a853533bb5d619a3d415e35b3217ad3a978ada Signed-off-by: Diego Sueiro <Diego.Sueiro@arm.com> Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>
252 lines
7.1 KiB
Text
252 lines
7.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
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/*
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* ARM Ltd. Fast Models
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*
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* Architecture Envelope Model (AEM) ARMv8-A
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* ARMAEMv8AMPCT
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*
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* RTSM_VE_AEMv8A.lisa
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*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <services/sdei_flags.h>
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#define LEVEL 0
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#define EDGE 2
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#define SDEI_NORMAL 0x70
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#define HIGHEST_SEC 0
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#include "rtsm_ve-motherboard.dtsi"
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/ {
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model = "FVP Base";
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compatible = "arm,fvp-base", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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stdout-path = "serial0:115200n8";
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#if (ENABLE_RME == 1)
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bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";
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#endif
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};
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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max-pwr-lvl = <2>;
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};
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#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
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firmware {
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#if SDEI_IN_FCONF
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sdei {
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compatible = "arm,sdei-1.0";
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method = "smc";
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private_event_count = <3>;
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shared_event_count = <3>;
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/*
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* Each event descriptor has typically 3 fields:
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* 1. Event number
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* 2. Interrupt number the event is bound to or
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* if event is dynamic, specified as SDEI_DYN_IRQ
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* 3. Bit map of event flags
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*/
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private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
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shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
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};
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#endif /* SDEI_IN_FCONF */
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#if SEC_INT_DESC_IN_FCONF
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sec_interrupts {
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compatible = "arm,secure_interrupt_desc";
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/* Number of G0 and G1 secure interrupts defined by the platform */
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g0_intr_cnt = <2>;
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g1s_intr_cnt = <9>;
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. Each interrupt property descriptor has 3 fields:
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* 1. Interrupt number
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* 2. Interrupt priority
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* 3. Type of interrupt (Edge or Level configured)
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*/
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g0_intr_desc = < 8 SDEI_NORMAL EDGE>,
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<14 HIGHEST_SEC EDGE>;
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g1s_intr_desc = < 9 HIGHEST_SEC EDGE>,
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<10 HIGHEST_SEC EDGE>,
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<11 HIGHEST_SEC EDGE>,
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<12 HIGHEST_SEC EDGE>,
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<13 HIGHEST_SEC EDGE>,
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<15 HIGHEST_SEC EDGE>,
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<29 HIGHEST_SEC LEVEL>,
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<56 HIGHEST_SEC LEVEL>,
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<57 HIGHEST_SEC LEVEL>;
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};
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#endif /* SEC_INT_DESC_IN_FCONF */
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};
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#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU_MAP
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <150>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <500>;
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exit-latency-us = <1000>;
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min-residency-us = <2500>;
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};
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};
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CPUS
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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#if (ENABLE_RME == 1)
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reg = <0x00000000 0x80000000 0 0x7C000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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#else
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reg = <0x00000000 0x80000000 0 0x7F000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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#endif
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Chipselect 2,00000000 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0x00000000 0x18000000 0 0x00800000>;
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no-map;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <100000000>;
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};
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timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <100000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x2a810000 0x100000>;
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x20000 0x10000>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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panel {
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compatible = "arm,rtsm-display";
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port {
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panel_in: endpoint {
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remote-endpoint = <&clcd_pads>;
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};
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};
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};
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bus@8000000 {
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 43 &gic 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 44 &gic 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 46 &gic 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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