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arm-trusted-firmware/plat/intel/soc/agilex5
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Sieu Mun Tang ce21a1a909 feat(intel): update Agilex5 DDR and IOSSM driver 
DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
2024-10-07 17:28:30 +02:00
..
include feat(intel): update Agilex5 DDR and IOSSM driver 2024-10-07 17:28:30 +02:00
soc feat(intel): update Agilex5 DDR and IOSSM driver 2024-10-07 17:28:30 +02:00
bl2_plat_setup.c feat(intel): update Agilex5 DDR and IOSSM driver 2024-10-07 17:28:30 +02:00
bl31_plat_setup.c fix(intel): add cache invalidation during BL31 initialization 2024-09-23 20:11:21 +02:00
platform.mk feat(intel): update Agilex5 DDR and IOSSM driver 2024-10-07 17:28:30 +02:00