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https://github.com/ARM-software/arm-trusted-firmware.git
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03020b6688
Add the required files to compile BL31 on STM32MP2. Update BL2 configuration to load BL31. The platform boots until BL31, but stops here as no other binaries are loaded as DDR is not initialized. At runtime, BL31 will use only the first half of the SYSRAM, the upper half will be used for non-secure DMA LLIs. To be sure nothing from this area is still in the cache, invalidate the upper SYSRAM before enabling BL31 cache. BL31 should then map only first half of the SYSRAM. But it must temporarily map the upper half read-only, as this is where we will retrieve BL2 parameters, used to fill registers for next boot stages. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: Ie91527a7a26625624b4b3c65fb6a0ca9dd355dbd
157 lines
5.4 KiB
C
157 lines
5.4 KiB
C
/*
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* Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#include "../stm32mp2_def.h"
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0xC00
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#define STM32MP_PRIMARY_CPU U(0x0)
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#define STM32MP_SECONDARY_CPU U(0x1)
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#define MAX_IO_DEVICES U(4)
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#define MAX_IO_HANDLES U(4)
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#define MAX_IO_BLOCK_DEVICES U(1)
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#define MAX_IO_MTD_DEVICES U(1)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CORE_COUNT U(2)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
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#define PLAT_MAX_PWR_LVL U(3)
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#define PLAT_MIN_SUSPEND_PWR_LVL U(2)
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#define PLAT_NUM_PWR_DOMAINS U(6)
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/* Local power state for power domains in Run state. */
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#define STM32MP_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. */
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#define STM32MP_LOCAL_STATE_RET U(1)
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#define STM32MP_LOCAL_STATE_LP U(2)
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#define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP
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/* Local power state for OFF/power-down. */
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#define STM32MP_LOCAL_STATE_OFF U(3)
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#define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF
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/* Macros to parse the state information from State-ID (recommended encoding) */
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#define PLAT_LOCAL_PSTATE_WIDTH U(4)
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#define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0)
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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/*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE STM32MP_BL2_BASE
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#define BL2_LIMIT (STM32MP_BL2_BASE + \
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STM32MP_BL2_SIZE)
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#define BL2_RO_BASE STM32MP_BL2_RO_BASE
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#define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \
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STM32MP_BL2_RO_SIZE)
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#define BL2_RW_BASE STM32MP_BL2_RW_BASE
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#define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \
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STM32MP_BL2_RW_SIZE)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#define BL31_BASE 0
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#define BL31_LIMIT STM32MP_BL31_SIZE
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/*******************************************************************************
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* BL33 specific defines.
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******************************************************************************/
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#define BL33_BASE STM32MP_BL33_BASE
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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/*
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* Secure Interrupt: based on the standard ARM mapping
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*/
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#define ARM_IRQ_SEC_PHY_TIMER U(29)
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#define ARM_IRQ_NON_SEC_SGI_0 U(0)
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#define ARM_IRQ_SEC_SGI_0 U(8)
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#define ARM_IRQ_SEC_SGI_1 U(9)
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#define ARM_IRQ_SEC_SGI_2 U(10)
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#define ARM_IRQ_SEC_SGI_3 U(11)
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#define ARM_IRQ_SEC_SGI_4 U(12)
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#define ARM_IRQ_SEC_SGI_5 U(13)
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#define ARM_IRQ_SEC_SGI_6 U(14)
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#define ARM_IRQ_SEC_SGI_7 U(15)
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/* Platform IRQ Priority */
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#define STM32MP_IRQ_SEC_SPI_PRIO U(0x10)
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLATFORM_G1S_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE)
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#define PLATFORM_G0_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE)
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#endif /* PLATFORM_DEF_H */
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