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https://github.com/ARM-software/arm-trusted-firmware.git
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03020b6688
Add the required files to compile BL31 on STM32MP2. Update BL2 configuration to load BL31. The platform boots until BL31, but stops here as no other binaries are loaded as DDR is not initialized. At runtime, BL31 will use only the first half of the SYSRAM, the upper half will be used for non-secure DMA LLIs. To be sure nothing from this area is still in the cache, invalidate the upper SYSRAM before enabling BL31 cache. BL31 should then map only first half of the SYSRAM. But it must temporarily map the upper half read-only, as this is where we will retrieve BL2 parameters, used to fill registers for next boot stages. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: Ie91527a7a26625624b4b3c65fb6a0ca9dd355dbd
85 lines
2 KiB
C
85 lines
2 KiB
C
/*
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* Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <common/bl_common.h>
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#include <drivers/st/stm32_console.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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bl_params_t *params_from_bl2;
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int ret;
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/*
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* Invalidate remaining data from second half of SYSRAM (used by BL2) as this area will
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* be later used as non-secure.
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*/
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inv_dcache_range(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
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STM32MP_SYSRAM_SIZE / 2U);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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#if USE_COHERENT_MEM
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/* Map coherent memory */
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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configure_mmu();
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/*
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* Map upper SYSRAM where bl_params_t are stored in BL2
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*/
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ret = mmap_add_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
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STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
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STM32MP_SYSRAM_SIZE / 2U, MT_RO_DATA | MT_SECURE);
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if (ret < 0) {
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ERROR("BL2 params area mapping: %d\n", ret);
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panic();
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}
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assert(arg0 != 0UL);
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params_from_bl2 = (bl_params_t *)arg0;
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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while (bl_params != NULL) {
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bl_params = bl_params->next_params_info;
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}
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ret = mmap_remove_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
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STM32MP_SYSRAM_SIZE / 2U);
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if (ret < 0) {
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ERROR("BL2 params area unmapping: %d\n", ret);
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panic();
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}
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}
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void bl31_plat_arch_setup(void)
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{
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}
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void bl31_platform_setup(void)
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{
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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return NULL;
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}
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