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86606eb51e
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE defines the platform specific cache line size, it is used to define the size of the cpu data structure CPU_DATA_SIZE aligned on cache line size. Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation of function '_cpu_data_by_index'. Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
158 lines
4.8 KiB
C
158 lines
4.8 KiB
C
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CPU_DATA_H__
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#define __CPU_DATA_H__
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#include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */
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#ifdef AARCH32
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#if CRASH_REPORTING
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#error "Crash reporting is not supported in AArch32"
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#endif
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#define CPU_DATA_CPU_OPS_PTR 0x0
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#define CPU_DATA_CRASH_BUF_OFFSET 0x4
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#else /* AARCH32 */
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/* Offsets for the cpu_data structure */
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#define CPU_DATA_CRASH_BUF_OFFSET 0x18
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/* need enough space in crash buffer to save 8 registers */
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#define CPU_DATA_CRASH_BUF_SIZE 64
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#define CPU_DATA_CPU_OPS_PTR 0x10
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#endif /* AARCH32 */
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#if CRASH_REPORTING
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#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
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CPU_DATA_CRASH_BUF_SIZE)
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#else
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#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
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#endif
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/* cpu_data size is the data size rounded up to the platform cache line size */
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#define CPU_DATA_SIZE (((CPU_DATA_CRASH_BUF_END + \
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CACHE_WRITEBACK_GRANULE - 1) / \
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CACHE_WRITEBACK_GRANULE) * \
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CACHE_WRITEBACK_GRANULE)
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#if ENABLE_RUNTIME_INSTRUMENTATION
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/* Temporary space to store PMF timestamps from assembly code */
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#define CPU_DATA_PMF_TS_COUNT 1
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#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
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#define CPU_DATA_PMF_TS0_IDX 0
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#endif
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#ifndef __ASSEMBLY__
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#include <arch_helpers.h>
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#include <cassert.h>
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#include <platform_def.h>
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#include <psci.h>
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#include <stdint.h>
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/* Offsets for the cpu_data structure */
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#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\
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(cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info)
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#if PLAT_PCPU_DATA_SIZE
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#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\
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(cpu_data_t, platform_cpu_data)
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#endif
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/*******************************************************************************
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* Function & variable prototypes
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******************************************************************************/
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/*******************************************************************************
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* Cache of frequently used per-cpu data:
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* Pointers to non-secure and secure security state contexts
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* Address of the crash stack
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* It is aligned to the cache line boundary to allow efficient concurrent
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* manipulation of these pointers on different cpus
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*
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* TODO: Add other commonly used variables to this (tf_issues#90)
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*
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* The data structure and the _cpu_data accessors should not be used directly
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* by components that have per-cpu members. The member access macros should be
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* used for this.
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******************************************************************************/
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typedef struct cpu_data {
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#ifndef AARCH32
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void *cpu_context[2];
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#endif
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uintptr_t cpu_ops_ptr;
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#if CRASH_REPORTING
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u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
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#endif
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#if ENABLE_RUNTIME_INSTRUMENTATION
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uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
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#endif
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struct psci_cpu_data psci_svc_cpu_data;
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#if PLAT_PCPU_DATA_SIZE
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uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
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#endif
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} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
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#if CRASH_REPORTING
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/* verify assembler offsets match data structures */
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CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
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(cpu_data_t, crash_buf),
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assert_cpu_data_crash_stack_offset_mismatch);
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#endif
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CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t),
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assert_cpu_data_size_mismatch);
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CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
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(cpu_data_t, cpu_ops_ptr),
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assert_cpu_data_cpu_ops_ptr_offset_mismatch);
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#if ENABLE_RUNTIME_INSTRUMENTATION
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CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof
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(cpu_data_t, cpu_data_pmf_ts[0]),
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assert_cpu_data_pmf_ts0_offset_mismatch);
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#endif
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struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
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#ifndef AARCH32
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/* Return the cpu_data structure for the current CPU. */
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static inline struct cpu_data *_cpu_data(void)
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{
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return (cpu_data_t *)read_tpidr_el3();
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}
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#else
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struct cpu_data *_cpu_data(void);
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#endif
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/**************************************************************************
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* APIs for initialising and accessing per-cpu data
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*************************************************************************/
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void init_cpu_data_ptr(void);
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void init_cpu_ops(void);
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#define get_cpu_data(_m) _cpu_data()->_m
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#define set_cpu_data(_m, _v) _cpu_data()->_m = _v
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#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
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#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v
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#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
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&(_cpu_data()->_m), \
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sizeof(_cpu_data()->_m))
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#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
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&(_cpu_data()->_m), \
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sizeof(_cpu_data()->_m))
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#define flush_cpu_data_by_index(_ix, _m) \
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flush_dcache_range((uintptr_t) \
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&(_cpu_data_by_index(_ix)->_m), \
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sizeof(_cpu_data_by_index(_ix)->_m))
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#endif /* __ASSEMBLY__ */
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#endif /* __CPU_DATA_H__ */
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