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https://github.com/ARM-software/arm-trusted-firmware.git
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3e61b2b543
Currently TF does not initialise the PMCR_EL0 register in the secure context or save/restore the register. In particular, the DP field may not be set to one to prohibit cycle counting in the secure state, even though event counting generally is prohibited via the default setting of MDCR_EL3.SMPE to 0. This patch initialises PMCR_EL0.DP to one in the secure state to prohibit cycle counting and also initialises other fields that have an architectually UNKNOWN reset value. Additionally, PMCR_EL0 is added to the list of registers that are saved and restored during a world switch. Similar changes are made for PMCR for the AArch32 execution state. NOTE: secure world code at lower ELs that assume other values in PMCR_EL0 will be impacted. Change-Id: Iae40e8c0a196d74053accf97063ebc257b4d2f3a Signed-off-by: David Cunado <david.cunado@arm.com>
121 lines
2.7 KiB
ArmAsm
121 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SMCC_MACROS_S__
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#define __SMCC_MACROS_S__
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#include <arch.h>
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/*
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* Macro to save the General purpose registers (r0 - r12), the banked
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* spsr, lr, sp registers and the `scr` register to the SMC context on entry
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* due a SMC call. The `lr` of the current mode (monitor) is expected to be
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* already saved. The `sp` must point to the `smc_ctx_t` to save to.
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* Additionally, also save the 'pmcr' register as this is updated whilst
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* executing in the secure world.
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*/
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.macro smcc_save_gp_mode_regs
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/* Save r0 - r12 in the SMC context */
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stm sp, {r0-r12}
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mov r0, sp
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add r0, r0, #SMC_CTX_SP_USR
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/* Save the banked registers including the current SPSR and LR */
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mrs r4, sp_usr
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mrs r5, lr_usr
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mrs r6, spsr_irq
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mrs r7, sp_irq
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mrs r8, lr_irq
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mrs r9, spsr_fiq
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mrs r10, sp_fiq
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mrs r11, lr_fiq
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mrs r12, spsr_svc
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stm r0!, {r4-r12}
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mrs r4, sp_svc
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mrs r5, lr_svc
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mrs r6, spsr_abt
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mrs r7, sp_abt
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mrs r8, lr_abt
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mrs r9, spsr_und
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mrs r10, sp_und
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mrs r11, lr_und
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mrs r12, spsr
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stm r0!, {r4-r12}
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/* lr_mon is already saved by caller */
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ldcopr r4, SCR
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str r4, [sp, #SMC_CTX_SCR]
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ldcopr r4, PMCR
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str r4, [sp, #SMC_CTX_PMCR]
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.endm
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/*
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* Macro to restore the `smc_ctx_t`, which includes the General purpose
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* registers and banked mode registers, and exit from the monitor mode.
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* r0 must point to the `smc_ctx_t` to restore from.
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*/
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.macro monitor_exit
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/*
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* Save the current sp and restore the smc context
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* pointer to sp which will be used for handling the
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* next SMC.
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*/
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str sp, [r0, #SMC_CTX_SP_MON]
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mov sp, r0
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/*
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* Restore SCR first so that we access the right banked register
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* when the other mode registers are restored.
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*/
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ldr r1, [r0, #SMC_CTX_SCR]
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stcopr r1, SCR
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isb
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/*
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* Restore the PMCR register.
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*/
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ldr r1, [r0, #SMC_CTX_PMCR]
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stcopr r1, PMCR
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/* Restore the banked registers including the current SPSR */
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add r1, r0, #SMC_CTX_SP_USR
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ldm r1!, {r4-r12}
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msr sp_usr, r4
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msr lr_usr, r5
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msr spsr_irq, r6
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msr sp_irq, r7
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msr lr_irq, r8
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msr spsr_fiq, r9
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msr sp_fiq, r10
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msr lr_fiq, r11
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msr spsr_svc, r12
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ldm r1!, {r4-r12}
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msr sp_svc, r4
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msr lr_svc, r5
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msr spsr_abt, r6
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msr sp_abt, r7
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msr lr_abt, r8
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msr spsr_und, r9
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msr sp_und, r10
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msr lr_und, r11
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/*
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* Use the `_fsxc` suffix explicitly to instruct the assembler
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* to update all the 32 bits of SPSR. Else, by default, the
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* assembler assumes `_fc` suffix which only modifies
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* f->[31:24] and c->[7:0] bits of SPSR.
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*/
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msr spsr_fsxc, r12
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/* Restore the LR */
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ldr lr, [r0, #SMC_CTX_LR_MON]
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/* Restore the rest of the general purpose registers */
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ldm r0, {r0-r12}
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eret
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.endm
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#endif /* __SMCC_MACROS_S__ */
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