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cc94e71b3a
The workarounds introduced in the three patches starting at
888eafa00b assumed that any powerdown
request will be (forced to be) terminal. This assumption can no longer
be the case for new CPUs so there is a need to revisit these older
cores. Since we may wake up, we now need to respect the workaround's
recommendation that the workaround needs to be reverted on wakeup. So do
exactly that.
Introduce a new helper to toggle bits in assembly. This allows us to
call the workaround twice, with the first call setting the workaround
and second undoing it. This is also used for gelas' an travis' powerdown
routines. This is so the same function can be called again
Also fix the condition in the cpu helper macro as it was subtly wrong
Change-Id: Iff9e5251dc9d8670d085d88c070f78991955e7c3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
142 lines
4.3 KiB
ArmAsm
142 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#include <lib/psci/psci.h>
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#include <platform_def.h>
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.globl psci_do_pwrdown_cache_maintenance
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.globl psci_do_pwrup_cache_maintenance
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.globl psci_power_down_wfi
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/* -----------------------------------------------------------------------
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* void psci_do_pwrdown_cache_maintenance(unsigned int power level);
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*
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* This function performs cache maintenance for the specified power
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* level. The levels of cache affected are determined by the power
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* level which is passed as the argument i.e. level 0 results
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* in a flush of the L1 cache. Both the L1 and L2 caches are flushed
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* for a higher power level.
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*
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* Additionally, this function also ensures that stack memory is correctly
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* flushed out to avoid coherency issues due to a change in its memory
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* attributes after the data cache is disabled.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrdown_cache_maintenance
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stp x29, x30, [sp,#-16]!
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stp x19, x20, [sp,#-16]!
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/* ---------------------------------------------
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* Invoke CPU-specific power down operations for
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* the appropriate level
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* ---------------------------------------------
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*/
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bl prepare_cpu_pwr_dwn
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/* ---------------------------------------------
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* Do stack maintenance by flushing the used
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* stack to the main memory and invalidating the
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* remainder.
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* ---------------------------------------------
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*/
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bl plat_get_my_stack
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in x1.
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* ---------------------------------------------
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*/
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mov x19, x0
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mov x1, sp
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sub x1, x0, x1
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mov x0, sp
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bl flush_dcache_range
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/* ---------------------------------------------
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* Calculate and store the size of the unused
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* stack memory in x1. Calculate and store the
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* stack base address in x0.
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* ---------------------------------------------
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*/
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sub x0, x19, #PLATFORM_STACK_SIZE
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sub x1, sp, x0
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bl inv_dcache_range
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ldp x19, x20, [sp], #16
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ldp x29, x30, [sp], #16
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ret
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endfunc psci_do_pwrdown_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_do_pwrup_cache_maintenance(void);
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*
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* This function performs cache maintenance after this cpu is powered up.
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* Currently, this involves managing the used stack memory before turning
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* on the data cache.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrup_cache_maintenance
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stp x29, x30, [sp,#-16]!
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/* ---------------------------------------------
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* Ensure any inflight stack writes have made it
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* to main memory.
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* ---------------------------------------------
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*/
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dmb st
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in x1. Calculate and store the
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* stack base address in x0.
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* ---------------------------------------------
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*/
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bl plat_get_my_stack
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mov x1, sp
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sub x1, x0, x1
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mov x0, sp
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bl inv_dcache_range
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/* ---------------------------------------------
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* Enable the data cache.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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orr x0, x0, #SCTLR_C_BIT
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msr sctlr_el3, x0
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isb
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ldp x29, x30, [sp], #16
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ret
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endfunc psci_do_pwrup_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_power_down_wfi(void);
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* This function is called to indicate to the power controller that it
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* is safe to power down this cpu. It should not exit the wfi and will
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* be released from reset upon power up.
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* -----------------------------------------------------------------------
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*/
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func psci_power_down_wfi
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apply_erratum cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597
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dsb sy // ensure write buffer empty
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1:
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wfi
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b 1b
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/*
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* in case the WFI wasn't terminal, we have to undo errata mitigations.
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* These will be smart enough to handle being called the same way
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*/
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apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219
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apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
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apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
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endfunc psci_power_down_wfi
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