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8fa5460708
Add basic CPU library code to support the Arcadia CPU. Change-Id: Iecb0634dc6dcb34e9b5fda4902335530d237cc43 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
64 lines
1.9 KiB
ArmAsm
64 lines
1.9 KiB
ArmAsm
/*
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* Copyright (c) 2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_arcadia.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-ARCADIA must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-ARCADIA supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_func_start cortex_arcadia
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_arcadia
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_arcadia_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_ARCADIA_CPUPWRCTLR_EL1, CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_arcadia_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-Arcadia specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_arcadia_regs, "aS"
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cortex_arcadia_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_arcadia_cpu_reg_dump
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adr x6, cortex_arcadia_regs
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mrs x8, CORTEX_ARCADIA_CPUECTLR_EL1
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ret
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endfunc cortex_arcadia_cpu_reg_dump
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declare_cpu_ops cortex_arcadia, CORTEX_ARCADIA_MIDR, \
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cortex_arcadia_reset_func, \
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cortex_arcadia_core_pwr_dwn
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