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db9ee83432
The errata framework has a helper to invoke workarounds, complete with a cpu rev_var check. We can use that directly instead of the apply_cpu_pwr_dwn_errata to save on some code, as well as an extra branch. It's also more readable. Also, apply_erratum invocation in cpu files don't need to check the rev_var as that was already done by the cpu_ops dispatcher for us to end up in the file. Finally, X2 erratum 2768515 only applies in the powerdown sequence, i.e. at runtime. It doesn't achieve anything at reset, so we can label it accordingly. Change-Id: I02f9dd7d0619feb54c870938ea186be5e3a6ca7b Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
140 lines
5.1 KiB
ArmAsm
140 lines
5.1 KiB
ArmAsm
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v2.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
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sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
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NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
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workaround_reset_end neoverse_v2, ERRATUM(2331132)
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check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
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workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597
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/* Disable retention control for WFI and WFE. */
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mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
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bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \
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#NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH
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bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \
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#NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH
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msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
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workaround_reset_end neoverse_v2, ERRATUM(2618597)
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check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553
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sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \
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NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH
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workaround_reset_end neoverse_v2, ERRATUM(2662553)
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check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105
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sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0
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workaround_reset_end neoverse_v2, ERRATUM(2719105)
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check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011
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sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55
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sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56
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workaround_reset_end neoverse_v2, ERRATUM(2743011)
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check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510
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sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47
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workaround_reset_end neoverse_v2, ERRATUM(2779510)
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check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1)
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workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
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check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-V2 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_v2
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_v2, CVE(2022,23960)
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check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func neoverse_v2_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV
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isb
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ret
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endfunc neoverse_v2_core_pwr_dwn
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cpu_reset_func_start neoverse_v2
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/* Disable speculative loads */
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msr SSBS, xzr
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#if NEOVERSE_Vx_EXTERNAL_LLC
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/* Some systems may have External LLC, core needs to be made aware */
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sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT
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#endif
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cpu_reset_func_end neoverse_v2
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/* ---------------------------------------------
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* This function provides Neoverse V2-
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* specific register information for crash
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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* and x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v2_regs, "aS"
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neoverse_v2_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v2_cpu_reg_dump
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adr x6, neoverse_v2_regs
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mrs x8, NEOVERSE_V2_CPUECTLR_EL1
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ret
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endfunc neoverse_v2_cpu_reg_dump
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declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
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neoverse_v2_reset_func, \
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neoverse_v2_core_pwr_dwn
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