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caae497dfc
These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
80 lines
1.4 KiB
C
80 lines
1.4 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* ZynqMP system level PM-API functions for pin control.
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*/
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#ifndef _PM_API_IOCTL_H_
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#define _PM_API_IOCTL_H_
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#include "pm_common.h"
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enum pm_ioctl_id {
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IOCTL_GET_RPU_OPER_MODE,
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IOCTL_SET_RPU_OPER_MODE,
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IOCTL_RPU_BOOT_ADDR_CONFIG,
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IOCTL_TCM_COMB_CONFIG,
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IOCTL_SET_TAPDELAY_BYPASS,
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IOCTL_SET_SGMII_MODE,
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IOCTL_SD_DLL_RESET,
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IOCTL_SET_SD_TAPDELAY,
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/* Ioctl for clock driver */
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IOCTL_SET_PLL_FRAC_MODE,
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IOCTL_GET_PLL_FRAC_MODE,
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IOCTL_SET_PLL_FRAC_DATA,
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IOCTL_GET_PLL_FRAC_DATA,
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};
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enum rpu_oper_mode {
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PM_RPU_MODE_LOCKSTEP,
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PM_RPU_MODE_SPLIT,
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};
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enum rpu_boot_mem {
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PM_RPU_BOOTMEM_LOVEC,
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PM_RPU_BOOTMEM_HIVEC,
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};
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enum rpu_tcm_comb {
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PM_RPU_TCM_SPLIT,
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PM_RPU_TCM_COMB,
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};
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enum tap_delay_signal_type {
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PM_TAPDELAY_NAND_DQS_IN,
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PM_TAPDELAY_NAND_DQS_OUT,
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PM_TAPDELAY_QSPI,
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PM_TAPDELAY_MAX,
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};
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enum tap_delay_bypass_ctrl {
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PM_TAPDELAY_BYPASS_DISABLE,
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PM_TAPDELAY_BYPASS_ENABLE,
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};
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enum sgmii_mode {
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PM_SGMII_DISABLE,
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PM_SGMII_ENABLE,
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};
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enum tap_delay_type {
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PM_TAPDELAY_INPUT,
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PM_TAPDELAY_OUTPUT,
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};
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enum dll_reset_type {
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PM_DLL_RESET_ASSERT,
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PM_DLL_RESET_RELEASE,
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PM_DLL_RESET_PULSE,
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};
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enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
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unsigned int ioctl_id,
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unsigned int arg1,
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unsigned int arg2,
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unsigned int *value);
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#endif /* _PM_API_IOCTL_H_ */
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