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https://github.com/ARM-software/arm-trusted-firmware.git
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caa84939a4
This patch uses the reworked exception handling support to handle runtime service requests through SMCs following the SMC calling convention. This is a giant commit since all the changes are inter-related. It does the following: 1. Replace the old exception handling mechanism with the new one 2. Enforce that SP_EL0 is used C runtime stacks. 3. Ensures that the cold and warm boot paths use the 'cpu_context' structure to program an ERET into the next lower EL. 4. Ensures that SP_EL3 always points to the next 'cpu_context' structure prior to an ERET into the next lower EL 5. Introduces a PSCI SMC handler which completes the use of PSCI as a runtime service Change-Id: I661797f834c0803d2c674d20f504df1b04c2b852 Co-authored-by: Achin Gupta <achin.gupta@arm.com>
187 lines
6 KiB
ArmAsm
187 lines
6 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bl_common.h>
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#include <platform.h>
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#include <arch.h>
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#include "cm_macros.S"
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.globl bl31_entrypoint
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.section .text, "ax"; .align 3
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/* -----------------------------------------------------
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* bl31_entrypoint() is the cold boot entrypoint,
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* executed only by the primary cpu.
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* -----------------------------------------------------
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*/
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bl31_entrypoint: ; .type bl31_entrypoint, %function
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/* ---------------------------------------------
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* BL2 has populated x0,x3,x4 with the opcode
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* indicating BL31 should be run, memory layout
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* of the trusted SRAM available to BL31 and
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* information about running the non-trusted
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* software already loaded by BL2.
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* ---------------------------------------------
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*/
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x1, early_exceptions
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msr vbar_el3, x1
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x1, cptr_el3
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bic w1, w1, #TCPAC_BIT
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bic w1, w1, #TTA_BIT
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bic w1, w1, #TFP_BIT
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msr cptr_el3, x1
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/* ---------------------------------------------
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* Enable the instruction cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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orr x1, x1, #SCTLR_I_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* Check the opcodes out of paranoia.
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* ---------------------------------------------
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*/
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mov x19, #RUN_IMAGE
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cmp x0, x19
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b.ne _panic
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mov x20, x3
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mov x21, x4
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/* ---------------------------------------------
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* This is BL31 which is expected to be executed
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* only by the primary cpu (at least for now).
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* So, make sure no secondary has lost its way.
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* ---------------------------------------------
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*/
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bl read_mpidr
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mov x19, x0
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bl platform_is_primary_cpu
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cbz x0, _panic
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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/* ---------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------
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*/
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msr spsel, #0
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/* --------------------------------------------
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* Give ourselves a small coherent stack to
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* ease the pain of initializing the MMU
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* --------------------------------------------
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*/
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mov x0, x19
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bl platform_set_coherent_stack
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/* ---------------------------------------------
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* Perform platform specific early arch. setup
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* ---------------------------------------------
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*/
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mov x0, x20
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mov x1, x21
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bl bl31_early_platform_setup
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bl bl31_plat_arch_setup
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/* ---------------------------------------------
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* Give ourselves a stack allocated in Normal
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* -IS-WBWA memory
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* ---------------------------------------------
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*/
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mov x0, x19
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bl platform_set_stack
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl31_main
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/* ---------------------------------------------
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* Use the more complex exception vectors now
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* that context management is setup. SP_EL3 is
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* pointing to a 'cpu_context' structure which
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* has an exception stack allocated. Since
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* we're just about to leave this EL with ERET,
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* we don't need an ISB here
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* ---------------------------------------------
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*/
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adr x1, runtime_exceptions
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msr vbar_el3, x1
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zero_callee_saved_regs
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b el3_exit
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_panic:
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wfi
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b _panic
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