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ca43b55d22
These APIs allow the GIC implementation to categorize interrupt numbers into SPIs, PPIs, and SGIs. The default implementations for GICv2 and GICv3 follows interrupt numbering as specified by the ARM GIC architecture. API documentation updated. Change-Id: Ia6aa379dc955994333232e6138f259535d4fa087 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
91 lines
2.9 KiB
C
91 lines
2.9 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __GIC_COMMON_H__
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#define __GIC_COMMON_H__
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/*******************************************************************************
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* GIC Distributor interface general definitions
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******************************************************************************/
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/* Constants to categorise interrupts */
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#define MIN_SGI_ID 0
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#define MIN_SEC_SGI_ID 8
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#define MIN_PPI_ID 16
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#define MIN_SPI_ID 32
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#define MAX_SPI_ID 1019
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#define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + 1)
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#define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID)
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/* Mask for the priority field common to all GIC interfaces */
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#define GIC_PRI_MASK 0xff
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/* Constant to indicate a spurious interrupt in all GIC versions */
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#define GIC_SPURIOUS_INTERRUPT 1023
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/* Constants to categorise priorities */
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#define GIC_HIGHEST_SEC_PRIORITY 0
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#define GIC_LOWEST_SEC_PRIORITY 127
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#define GIC_HIGHEST_NS_PRIORITY 128
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#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */
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/*******************************************************************************
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* GIC Distributor interface register offsets that are common to GICv3 & GICv2
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******************************************************************************/
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#define GICD_CTLR 0x0
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#define GICD_TYPER 0x4
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#define GICD_IIDR 0x8
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#define GICD_IGROUPR 0x80
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#define GICD_ISENABLER 0x100
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#define GICD_ICENABLER 0x180
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#define GICD_ISPENDR 0x200
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#define GICD_ICPENDR 0x280
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#define GICD_ISACTIVER 0x300
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#define GICD_ICACTIVER 0x380
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#define GICD_IPRIORITYR 0x400
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#define GICD_ICFGR 0xc00
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#define GICD_NSACR 0xe00
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/* GICD_CTLR bit definitions */
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#define CTLR_ENABLE_G0_SHIFT 0
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#define CTLR_ENABLE_G0_MASK 0x1
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#define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT)
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/*******************************************************************************
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* GIC Distributor interface register constants that are common to GICv3 & GICv2
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******************************************************************************/
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#define PIDR2_ARCH_REV_SHIFT 4
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#define PIDR2_ARCH_REV_MASK 0xf
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/* GICv3 revision as reported by the PIDR2 register */
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#define ARCH_REV_GICV3 0x3
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/* GICv2 revision as reported by the PIDR2 register */
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#define ARCH_REV_GICV2 0x2
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#define IGROUPR_SHIFT 5
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#define ISENABLER_SHIFT 5
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#define ICENABLER_SHIFT ISENABLER_SHIFT
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#define ISPENDR_SHIFT 5
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#define ICPENDR_SHIFT ISPENDR_SHIFT
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#define ISACTIVER_SHIFT 5
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#define ICACTIVER_SHIFT ISACTIVER_SHIFT
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#define IPRIORITYR_SHIFT 2
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#define ICFGR_SHIFT 4
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#define NSACR_SHIFT 4
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/* GICD_TYPER shifts and masks */
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#define TYPER_IT_LINES_NO_SHIFT 0
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#define TYPER_IT_LINES_NO_MASK 0x1f
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/* Value used to initialize Normal world interrupt priorities four at a time */
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#define GICD_IPRIORITYR_DEF_VAL \
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(GIC_HIGHEST_NS_PRIORITY | \
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(GIC_HIGHEST_NS_PRIORITY << 8) | \
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(GIC_HIGHEST_NS_PRIORITY << 16) | \
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(GIC_HIGHEST_NS_PRIORITY << 24))
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#endif /* __GIC_COMMON_H__ */
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