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f000744e0f
The set_cnt_freq() function is introduced to configure the counter frequency register.If the counter frequency register is zero, it writes the output of plat_get_syscnt_freq2() the cpu_clocks to the counter frequency register. According to the design specifications provided for Versal, the lpd_data.cdo file contains a mask_write operation for register 0xFF140020 (base_frequency_ID_register) to set it to 0x5f5e100, configuring it for a 100MHz clock frequency. Reading the value of the IOU_SCNTRS_BASE_FREQ register using mmio_read_32() to determine the counter frequency. If the counter frequency is zero, the system will set the default CPU clocks constants in TF-A and displays message. However, if the counter frequency is non-zero, the program will return the value stored in the IOU_SCNTRS_BASE_FREQ register. The issue lies in dcc_status_timeout(),function verifying timeout status, particularly within timeout_cnt_us2cnt(), converting microseconds to counter ticks using read_cntfrq_el0(), which returns zero. timeout_elapsed() then checks if the current counter from read_cntpct_el0()exceeds the expiration count, denoting timeout. After the function set_cnt_freq() writes into the counter frequency register, the function timeout_cnt_us2cnt() is used to obtain the appropriate counter ticks. Subsequently, the function timeout_elapsed() checks whether the current counter value read_cntpct_el0() has exceeded the specified expiration count. If it has, this indicates that the timeout has lapsed. Change-Id: I8f2f4d804b5aefa6f92083d831a5ebfade384294 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
13 lines
234 B
C
13 lines
234 B
C
/*
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* Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_CLKFUNC_H
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#define PLAT_CLKFUNC_H
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void set_cnt_freq(void);
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#endif /* PLAT_CLKFUNC_H */
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