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https://github.com/ARM-software/arm-trusted-firmware.git
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97ef53052b
In preparation for RPi 5 support, which will reuse most of the RPi 4 logic except for DTB patching. Change-Id: I6f6ef96933711a1798757a3389adae1b8ee3de6c Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
/*
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* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <common/fdt_fixup.h>
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#include <common/fdt_wrappers.h>
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#include <rpi_shared.h>
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/*
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* Remove the FDT /memreserve/ entry that covers the region at the very
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* beginning of memory (if that exists). This is where the secondaries
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* originally spin, but we pull them out there.
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* Having overlapping /reserved-memory and /memreserve/ regions confuses
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* the Linux kernel, so we need to get rid of this one.
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*/
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static void remove_spintable_memreserve(void *dtb)
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{
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uint64_t addr, size;
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int regions = fdt_num_mem_rsv(dtb);
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int i;
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for (i = 0; i < regions; i++) {
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if (fdt_get_mem_rsv(dtb, i, &addr, &size) != 0) {
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return;
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}
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if (size == 0U) {
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return;
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}
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/* We only look for the region at the beginning of DRAM. */
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if (addr != 0U) {
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continue;
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}
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/*
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* Currently the region in the existing DTs is exactly 4K
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* in size. Should this value ever change, there is probably
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* a reason for that, so inform the user about this.
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*/
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if (size == 4096U) {
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fdt_del_mem_rsv(dtb, i);
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return;
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}
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WARN("Keeping unknown /memreserve/ region at 0, size: %" PRId64 "\n",
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size);
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}
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}
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static void rpi4_prepare_dtb(void)
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{
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void *dtb = (void *)rpi4_get_dtb_address();
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uint32_t gic_int_prop[3];
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int ret, offs;
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/* Return if no device tree is detected */
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if (fdt_check_header(dtb) != 0)
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return;
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ret = fdt_open_into(dtb, dtb, 0x100000);
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if (ret < 0) {
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ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
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return;
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}
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if (dt_add_psci_node(dtb)) {
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ERROR("Failed to add PSCI Device Tree node\n");
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return;
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}
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if (dt_add_psci_cpu_enable_methods(dtb)) {
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ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
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return;
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}
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/*
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* Remove the original reserved region (used for the spintable), and
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* replace it with a region describing the whole of Trusted Firmware.
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*/
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remove_spintable_memreserve(dtb);
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if (fdt_add_reserved_memory(dtb, "atf@0", 0, 0x80000))
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WARN("Failed to add reserved memory nodes to DT.\n");
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offs = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-400");
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gic_int_prop[0] = cpu_to_fdt32(1); // PPI
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gic_int_prop[1] = cpu_to_fdt32(9); // PPI #9
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gic_int_prop[2] = cpu_to_fdt32(0x0f04); // all cores, level high
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fdt_setprop(dtb, offs, "interrupts", gic_int_prop, 12);
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offs = fdt_path_offset(dtb, "/chosen");
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fdt_setprop_string(dtb, offs, "stdout-path", "serial0");
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ret = fdt_pack(dtb);
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if (ret < 0)
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ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
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clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
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INFO("Changed device tree to advertise PSCI.\n");
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}
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void plat_rpi_bl31_custom_setup(void)
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{
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rpi4_prepare_dtb();
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}
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