mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
99bc6cf518
When RME is enabled on SBSA, the RMM is located at the start of the NS RAM and the device tree after it. This patch adjust the DT memory start address so that anyone reading it has an accurate view of the system configuration. Change-Id: I32ca63a78d68831faf2c65ad60a45c841b7cbada Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
464 lines
10 KiB
C
464 lines
10 KiB
C
/*
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* Copyright (c) 2024-2025, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/fdt_wrappers.h>
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#include <libfdt.h>
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#include <sbsa_platform.h>
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#include "qemu_private.h"
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/* default platform version is 0.0 */
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static int platform_version_major;
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static int platform_version_minor;
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static uint64_t gic_its_addr;
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static struct qemu_platform_info dynamic_platform_info;
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void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
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/*
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* QEMU provides us with minimal information about hardware platform using
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* minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
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* a firmware DeviceTree.
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*
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* It is information passed from QEMU to describe the information a hardware
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* platform would have other mechanisms to discover at runtime, that are
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* affected by the QEMU command line.
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*
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* Ultimately this device tree will be replaced by IPC calls to an emulated SCP.
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* And when we do that, we won't then have to rewrite Normal world firmware to
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* cope.
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*/
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static void read_cpu_topology_from_dt(void *dtb)
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{
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int node;
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/*
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* QEMU gives us this DeviceTree node when we config:
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* -smp 16,sockets=2,clusters=2,cores=2,threads=2
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*
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* topology {
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* threads = <0x02>;
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* cores = <0x02>;
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* clusters = <0x02>;
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* sockets = <0x02>;
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* };
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*/
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node = fdt_path_offset(dtb, "/cpus/topology");
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if (node > 0) {
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dynamic_platform_info.cpu_topo.sockets =
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fdt_read_uint32_default(dtb, node, "sockets", 0);
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dynamic_platform_info.cpu_topo.clusters =
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fdt_read_uint32_default(dtb, node, "clusters", 0);
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dynamic_platform_info.cpu_topo.cores =
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fdt_read_uint32_default(dtb, node, "cores", 0);
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dynamic_platform_info.cpu_topo.threads =
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fdt_read_uint32_default(dtb, node, "threads", 0);
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}
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INFO("Cpu topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
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dynamic_platform_info.cpu_topo.sockets,
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dynamic_platform_info.cpu_topo.clusters,
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dynamic_platform_info.cpu_topo.cores,
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dynamic_platform_info.cpu_topo.threads);
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}
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static void read_cpuinfo_from_dt(void *dtb)
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{
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int node;
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int prev;
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int cpu = 0;
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uintptr_t mpidr;
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/*
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* QEMU gives us this DeviceTree node:
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* numa-node-id entries are only when NUMA config is used
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*
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* cpus {
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* #size-cells = <0x00>;
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* #address-cells = <0x02>;
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*
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* cpu@0 {
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* numa-node-id = <0x00>;
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* reg = <0x00 0x00>;
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* };
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*
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* cpu@1 {
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* numa-node-id = <0x03>;
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* reg = <0x00 0x01>;
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* };
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* };
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*/
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node = fdt_path_offset(dtb, "/cpus");
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if (node < 0) {
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ERROR("No information about cpus in DeviceTree.\n");
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panic();
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}
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/*
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* QEMU numbers cpus from 0 and there can be /cpus/cpu-map present so we
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* cannot use fdt_first_subnode() here
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*/
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node = fdt_path_offset(dtb, "/cpus/cpu@0");
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while (node > 0) {
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if (fdt_getprop(dtb, node, "reg", NULL)) {
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fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL);
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} else {
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ERROR("Incomplete information for cpu %d in DeviceTree.\n", cpu);
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panic();
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}
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dynamic_platform_info.cpu[cpu].mpidr = mpidr;
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dynamic_platform_info.cpu[cpu].nodeid =
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fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
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INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu,
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dynamic_platform_info.cpu[cpu].nodeid, mpidr);
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cpu++;
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prev = node;
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node = fdt_next_subnode(dtb, prev);
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}
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dynamic_platform_info.num_cpus = cpu;
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INFO("Found %d cpus\n", dynamic_platform_info.num_cpus);
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read_cpu_topology_from_dt(dtb);
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}
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static void read_meminfo_from_dt(void *dtb)
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{
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const fdt32_t *prop;
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const char *type;
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int prev, node;
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int len;
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uint32_t memnode = 0;
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uint32_t higher_value, lower_value;
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uint64_t cur_base, cur_size;
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/*
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* QEMU gives us this DeviceTree node:
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*
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* memory@100c0000000 {
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* numa-node-id = <0x01>;
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* reg = <0x100 0xc0000000 0x00 0x40000000>;
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* device_type = "memory";
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* };
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*
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* memory@10000000000 {
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* numa-node-id = <0x00>;
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* reg = <0x100 0x00 0x00 0xc0000000>;
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* device_type = "memory";
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* }
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*/
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for (prev = 0;; prev = node) {
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node = fdt_next_node(dtb, prev, NULL);
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if (node < 0) {
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break;
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}
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type = fdt_getprop(dtb, node, "device_type", &len);
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if (type && strncmp(type, "memory", len) == 0) {
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dynamic_platform_info.memory[memnode].nodeid =
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fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
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/*
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* Get the 'reg' property of this node and
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* assume two 8 bytes for base and size.
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*/
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prop = fdt_getprop(dtb, node, "reg", &len);
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if (prop != 0 && len == (2 * sizeof(int64_t))) {
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higher_value = fdt32_to_cpu(*prop);
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lower_value = fdt32_to_cpu(*(prop + 1));
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cur_base = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32);
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higher_value = fdt32_to_cpu(*(prop + 2));
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lower_value = fdt32_to_cpu(*(prop + 3));
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cur_size = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32);
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dynamic_platform_info.memory[memnode].addr_base = cur_base;
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dynamic_platform_info.memory[memnode].addr_size = cur_size;
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INFO("RAM %d: node-id: %d, address: 0x%lx - 0x%lx\n",
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memnode,
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dynamic_platform_info.memory[memnode].nodeid,
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dynamic_platform_info.memory[memnode].addr_base,
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dynamic_platform_info.memory[memnode].addr_base +
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dynamic_platform_info.memory[memnode].addr_size - 1);
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}
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memnode++;
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}
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}
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dynamic_platform_info.num_memnodes = memnode;
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}
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static void read_platform_config_from_dt(void *dtb)
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{
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int node;
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const fdt64_t *data;
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int err;
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uintptr_t gicd_base;
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uintptr_t gicr_base;
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/*
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* QEMU gives us this DeviceTree node:
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*
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* intc {
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* reg = < 0x00 0x40060000 0x00 0x10000
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* 0x00 0x40080000 0x00 0x4000000>;
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* its {
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* reg = <0x00 0x44081000 0x00 0x20000>;
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* };
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* };
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*/
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node = fdt_path_offset(dtb, "/intc");
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if (node < 0) {
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return;
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}
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data = fdt_getprop(dtb, node, "reg", NULL);
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if (data == NULL) {
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return;
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}
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err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL);
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if (err < 0) {
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ERROR("Failed to read GICD reg property of GIC node\n");
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return;
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}
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INFO("GICD base = 0x%lx\n", gicd_base);
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err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL);
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if (err < 0) {
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ERROR("Failed to read GICR reg property of GIC node\n");
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return;
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}
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INFO("GICR base = 0x%lx\n", gicr_base);
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sbsa_set_gic_bases(gicd_base, gicr_base);
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node = fdt_path_offset(dtb, "/intc/its");
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if (node < 0) {
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return;
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}
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err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL);
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if (err < 0) {
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ERROR("Failed to read GICI reg property of GIC node\n");
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return;
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}
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INFO("GICI base = 0x%lx\n", gic_its_addr);
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}
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static void read_platform_version(void *dtb)
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{
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int node;
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node = fdt_path_offset(dtb, "/");
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if (node >= 0) {
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platform_version_major =
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fdt_read_uint32_default(dtb, node, "machine-version-major", 0);
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platform_version_minor =
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fdt_read_uint32_default(dtb, node, "machine-version-minor", 0);
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}
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}
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#if !ENABLE_RME
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static int set_system_memory_base(void *dtb, uintptr_t new_base)
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{
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(void)dtb;
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(void)new_base;
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return 0;
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}
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#else /* !ENABLE_RME */
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static int set_system_memory_base(void *dtb, uintptr_t new_base)
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{
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uint64_t cur_base, cur_size, new_size, delta;
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int len, prev, node, ret;
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const fdt32_t *prop;
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uint32_t node_id;
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const char *type;
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fdt64_t new[2];
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/*
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* QEMU gives us this DeviceTree node:
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*
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* memory@100c0000000 {
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* numa-node-id = <0x01>;
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* reg = <0x100 0xc0000000 0x00 0x40000000>;
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* device_type = "memory";
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* };
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*
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* memory@10000000000 {
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* numa-node-id = <0x00>;
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* reg = <0x100 0x00 0x00 0xc0000000>;
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* device_type = "memory";
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* }
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*/
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for (prev = 0;; prev = node) {
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node = fdt_next_node(dtb, prev, NULL);
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if (node < 0) {
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return node;
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}
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type = fdt_getprop(dtb, node, "device_type", &len);
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if (type && strncmp(type, "memory", len) == 0) {
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/*
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* We are looking for numa node 0, i.e the start of the
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* system memory. If a "numa-node-id" doesn't exists we
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* take the first one.
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*/
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node_id = fdt_read_uint32_default(dtb, node,
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"numa-node-id", 0);
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if (node_id == 0) {
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break;
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}
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}
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}
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/*
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* Get the 'reg' property of this node and
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* assume two 8 bytes for base and size.
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*/
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prop = fdt_getprop(dtb, node, "reg", &len);
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if (!prop || len < 0) {
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return len;
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}
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if (len != (2 * sizeof(uint64_t))) {
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return -FDT_ERR_BADVALUE;
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}
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ret = fdt_get_reg_props_by_index(dtb, node, 0, &cur_base, &cur_size);
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if (ret < 0)
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return ret;
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/*
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* @cur_base is the base of the NS RAM given to us by QEMU, we can't
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* go lower than that.
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*/
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if (new_base < cur_base) {
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return -FDT_ERR_BADVALUE;
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}
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if (new_base == cur_base) {
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return 0;
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}
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/*
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* The new base is higher than the base set by QEMU, i.e we are moving
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* the base memory up and shrinking the size.
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*/
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delta = (size_t)(new_base - cur_base);
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/*
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* Make sure the new base is still within the base memory node, i.e
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* the base memory node is big enough for the RMM.
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*/
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if (delta >= cur_size) {
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ERROR("Not enough space in base memory node for RMM\n");
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return -FDT_ERR_BADVALUE;
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}
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new_size = cur_size - delta;
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new[0] = cpu_to_fdt64(new_base);
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new[1] = cpu_to_fdt64(new_size);
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ret = fdt_setprop(dtb, node, "reg", new, len);
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if (ret < 0) {
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return ret;
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}
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return fdt_pack(dtb);
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}
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#endif /* !ENABLE_RME */
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void sbsa_platform_init(void)
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{
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/* Read DeviceTree data before MMU is enabled */
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void *dtb = plat_qemu_dt_runtime_address();
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int err;
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err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE);
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if (err < 0) {
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ERROR("Invalid Device Tree at %p: error %d\n", dtb, err);
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return;
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}
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err = fdt_check_header(dtb);
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if (err < 0) {
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ERROR("Invalid DTB file passed\n");
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return;
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}
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read_platform_version(dtb);
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INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor);
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if (set_system_memory_base(dtb, NS_DRAM0_BASE)) {
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ERROR("Failed to set system memory in Device Tree\n");
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return;
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}
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read_platform_config_from_dt(dtb);
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read_cpuinfo_from_dt(dtb);
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read_meminfo_from_dt(dtb);
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}
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int sbsa_platform_version_major(void)
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{
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return platform_version_major;
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}
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int sbsa_platform_version_minor(void)
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{
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return platform_version_minor;
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}
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uint32_t sbsa_platform_num_cpus(void)
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{
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return dynamic_platform_info.num_cpus;
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}
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uint32_t sbsa_platform_num_memnodes(void)
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{
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return dynamic_platform_info.num_memnodes;
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}
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uint64_t sbsa_platform_gic_its_addr(void)
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{
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return gic_its_addr;
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}
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struct platform_cpu_data sbsa_platform_cpu_node(uint64_t index)
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{
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return dynamic_platform_info.cpu[index];
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}
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struct platform_memory_data sbsa_platform_memory_node(uint64_t index)
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{
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return dynamic_platform_info.memory[index];
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}
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struct platform_cpu_topology sbsa_platform_cpu_topology(void)
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{
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return dynamic_platform_info.cpu_topo;
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}
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