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https://github.com/ARM-software/arm-trusted-firmware.git
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S32G274ARDB2 is a development board to showcase the capabilities of the S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs of DDR, accelerators for automotive networking and many other peripherals. The added support is minimal and only includes the BL2 stage, with no MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies BL31 and BL33 from FIP to their designated addresses. Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842 Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> Signed-off-by: Dan Nica <dan.nica@nxp.com> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
135 lines
2.8 KiB
C
135 lines
2.8 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_fip.h>
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#include <drivers/io/io_memmap.h>
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#include <plat/common/platform.h>
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#include <tools_share/firmware_image_package.h>
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#include <plat_io_storage.h>
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struct plat_io_policy {
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uintptr_t *dev_handle;
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uintptr_t image_spec;
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int (*check)(const uintptr_t spec);
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};
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static int open_memmap(const uintptr_t spec);
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static int open_fip(const uintptr_t spec);
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static uintptr_t fip_dev_handle;
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static uintptr_t memmap_dev_handle;
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static int open_memmap(const uintptr_t spec)
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{
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uintptr_t temp_handle = 0U;
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int result;
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result = io_dev_init(memmap_dev_handle, (uintptr_t)0);
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if (result != 0) {
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return result;
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}
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result = io_open(memmap_dev_handle, spec, &temp_handle);
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if (result == 0) {
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(void)io_close(temp_handle);
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}
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return result;
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}
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static int open_fip(const uintptr_t spec)
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{
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uintptr_t temp_handle = 0U;
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int result;
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/* See if a Firmware Image Package is available */
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result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
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if (result != 0) {
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return result;
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}
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result = io_open(fip_dev_handle, spec, &temp_handle);
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if (result == 0) {
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(void)io_close(temp_handle);
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}
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return result;
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}
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void plat_s32g2_io_setup(void)
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{
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static const io_dev_connector_t *memmap_dev_con;
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static const io_dev_connector_t *fip_dev_con;
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int result __unused;
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result = register_io_dev_memmap(&memmap_dev_con);
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assert(result == 0);
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result = io_dev_open(memmap_dev_con, (uintptr_t)0,
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&memmap_dev_handle);
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assert(result == 0);
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result = register_io_dev_fip(&fip_dev_con);
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assert(result == 0);
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result = io_dev_open(fip_dev_con, (uintptr_t)0,
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&fip_dev_handle);
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assert(result == 0);
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}
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int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
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uintptr_t *image_spec)
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{
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static const io_block_spec_t fip_block_spec = {
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.offset = S32G_FIP_BASE,
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.length = S32G_FIP_SIZE,
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};
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static const io_uuid_spec_t bl31_uuid_spec = {
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.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
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};
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static const io_uuid_spec_t bl33_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
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};
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static const struct plat_io_policy policies[BL33_IMAGE_ID + 1] = {
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[FIP_IMAGE_ID] = {
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.dev_handle = &memmap_dev_handle,
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.image_spec = (uintptr_t)&fip_block_spec,
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.check = open_memmap,
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},
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[BL31_IMAGE_ID] = {
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.dev_handle = &fip_dev_handle,
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.image_spec = (uintptr_t)&bl31_uuid_spec,
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.check = open_fip,
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},
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[BL33_IMAGE_ID] = {
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.dev_handle = &fip_dev_handle,
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.image_spec = (uintptr_t)&bl33_uuid_spec,
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.check = open_fip,
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},
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};
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const struct plat_io_policy *policy;
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int result;
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assert(image_id < ARRAY_SIZE(policies));
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policy = &policies[image_id];
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result = policy->check(policy->image_spec);
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assert(result == 0);
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*image_spec = policy->image_spec;
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*dev_handle = *policy->dev_handle;
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return result;
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}
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