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https://github.com/ARM-software/arm-trusted-firmware.git
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0f33f50e21
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2 raised from kernel (> 5.4). As part of first cold boot, DDR training data is stored in NV storage. As part of this SMC handling, following things are done: - DDR is put in self-refresh mode to retain the content of DDR. - Reset cause is saved. - Reset is triggered. On next boot to last warm-reset, DDR training is restored from the NV storage. Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I8e4fb0824887af49e959c93825e2ab0ba887fc9d
121 lines
2.6 KiB
C
121 lines
2.6 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <errno.h>
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#include <common/debug.h>
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#include <ddr.h>
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#ifndef NXP_COINED_BB
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#include <flash_info.h>
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#include <fspi.h>
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#include <fspi_api.h>
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#endif
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#ifdef NXP_COINED_BB
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#include <snvs.h>
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#endif
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#include <plat_nv_storage.h>
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#include "plat_warm_rst.h"
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#include "platform_def.h"
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#if defined(IMAGE_BL2)
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uint32_t is_warm_boot(void)
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{
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uint32_t ret = mmio_read_32(NXP_RESET_ADDR + RST_RSTRQSR1_OFFSET)
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& ~(RSTRQSR1_SWRR);
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const nv_app_data_t *nv_app_data = get_nv_data();
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if (ret == 0U) {
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INFO("Not a SW(Warm) triggered reset.\n");
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return 0U;
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}
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ret = (nv_app_data->warm_rst_flag == WARM_BOOT_SUCCESS) ? 1 : 0;
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if (ret != 0U) {
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INFO("Warm Reset was triggered..\n");
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} else {
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INFO("Warm Reset was not triggered..\n");
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}
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return ret;
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}
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#endif
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#if defined(IMAGE_BL31)
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int prep_n_execute_warm_reset(void)
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{
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#ifdef NXP_COINED_BB
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#if !TRUSTED_BOARD_BOOT
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snvs_disable_zeroize_lp_gpr();
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#endif
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#else
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int ret;
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uint8_t warm_reset = WARM_BOOT_SUCCESS;
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ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);
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if (ret != 0) {
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ERROR("Failed to initialized driver flexspi-nor.\n");
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ERROR("exiting warm-reset request.\n");
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return PSCI_E_INTERN_FAIL;
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}
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/* Sector starting from NV_STORAGE_BASE_ADDR is already
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* erased for writing.
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*/
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#if (ERLY_WRM_RST_FLG_FLSH_UPDT)
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ret = xspi_write((uint32_t)NV_STORAGE_BASE_ADDR,
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&warm_reset,
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sizeof(warm_reset));
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#else
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/* Preparation for writing the Warm reset flag. */
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ret = xspi_wren((uint32_t)NV_STORAGE_BASE_ADDR);
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/* IP Control Register0 - SF Address to be read */
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fspi_out32((NXP_FLEXSPI_ADDR + FSPI_IPCR0),
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(uint32_t) NV_STORAGE_BASE_ADDR);
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while ((fspi_in32(NXP_FLEXSPI_ADDR + FSPI_INTR) &
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FSPI_INTR_IPTXWE_MASK) == 0) {
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;
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}
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/* Write TX FIFO Data Register */
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fspi_out32(NXP_FLEXSPI_ADDR + FSPI_TFDR, (uint32_t) warm_reset);
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fspi_out32(NXP_FLEXSPI_ADDR + FSPI_INTR, FSPI_INTR_IPTXWE);
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/* IP Control Register1 - SEQID_WRITE operation, Size = 1 Byte */
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fspi_out32(NXP_FLEXSPI_ADDR + FSPI_IPCR1,
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(uint32_t)(FSPI_WRITE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) |
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(uint16_t) sizeof(warm_reset));
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/* Trigger XSPI-IP-Write cmd only if:
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* - Putting DDR in-self refresh mode is successfully.
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* to complete the writing of the warm-reset flag
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* to flash.
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*
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* This code is as part of assembly.
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*/
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#endif
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#endif
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INFO("Doing DDR Self refresh.\n");
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_soc_sys_warm_reset();
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/* Expected behaviour is to do the power cycle */
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while (1 != 0)
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;
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return -1;
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}
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#endif
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