mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-21 03:54:34 +00:00
b759727f59
Added IFC Nor and NAN flash as boot IO devices. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ie1b87174d9c08d4e32138066b007fef6f8e3c5dd
556 lines
12 KiB
C
556 lines
12 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <endian.h>
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#include <string.h>
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#include <common/debug.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/io/io_block.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_fip.h>
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#include <drivers/io/io_memmap.h>
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#include <drivers/io/io_storage.h>
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#ifdef FLEXSPI_NOR_BOOT
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#include <flexspi_nor.h>
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#endif
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#if defined(NAND_BOOT)
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#include <ifc_nand.h>
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#endif
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#if defined(NOR_BOOT)
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#include <ifc_nor.h>
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#endif
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#if defined(QSPI_BOOT)
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#include <qspi.h>
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#endif
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#if defined(SD_BOOT) || defined(EMMC_BOOT)
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#include <sd_mmc.h>
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#endif
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#include <tools_share/firmware_image_package.h>
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#ifdef CONFIG_DDR_FIP_IMAGE
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#include <ddr_io_storage.h>
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#endif
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#ifdef POLICY_FUSE_PROVISION
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#include <fuse_io.h>
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#endif
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#include "plat_common.h"
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#include "platform_def.h"
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uint32_t fip_device;
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/* IO devices */
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uintptr_t backend_dev_handle;
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static const io_dev_connector_t *fip_dev_con;
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static uintptr_t fip_dev_handle;
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static const io_dev_connector_t *backend_dev_con;
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static io_block_spec_t fip_block_spec = {
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.offset = PLAT_FIP_OFFSET,
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.length = PLAT_FIP_MAX_SIZE
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};
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static const io_uuid_spec_t bl2_uuid_spec = {
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.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
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};
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static const io_uuid_spec_t fuse_bl2_uuid_spec = {
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.uuid = UUID_SCP_FIRMWARE_SCP_BL2,
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};
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static const io_uuid_spec_t bl31_uuid_spec = {
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.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
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};
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static const io_uuid_spec_t bl32_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32,
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};
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static const io_uuid_spec_t bl33_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
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};
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static const io_uuid_spec_t tb_fw_config_uuid_spec = {
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.uuid = UUID_TB_FW_CONFIG,
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};
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static const io_uuid_spec_t hw_config_uuid_spec = {
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.uuid = UUID_HW_CONFIG,
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};
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#if TRUSTED_BOARD_BOOT
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static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_BOOT_FW_CERT,
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};
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static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_KEY_CERT,
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};
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static const io_uuid_spec_t fuse_key_cert_uuid_spec = {
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.uuid = UUID_SCP_FW_KEY_CERT,
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};
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static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
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.uuid = UUID_SOC_FW_KEY_CERT,
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};
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static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
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};
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static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
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};
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static const io_uuid_spec_t fuse_cert_uuid_spec = {
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.uuid = UUID_SCP_FW_CONTENT_CERT,
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};
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static const io_uuid_spec_t soc_fw_cert_uuid_spec = {
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.uuid = UUID_SOC_FW_CONTENT_CERT,
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};
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static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
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};
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static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
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};
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#endif /* TRUSTED_BOARD_BOOT */
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static int open_fip(const uintptr_t spec);
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struct plat_io_policy {
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uintptr_t *dev_handle;
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uintptr_t image_spec;
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int (*check)(const uintptr_t spec);
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};
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/* By default, ARM platforms load images from the FIP */
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static const struct plat_io_policy policies[] = {
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[FIP_IMAGE_ID] = {
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&backend_dev_handle,
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(uintptr_t)&fip_block_spec,
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open_backend
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},
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[BL2_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl2_uuid_spec,
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open_fip
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},
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[SCP_BL2_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&fuse_bl2_uuid_spec,
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open_fip
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},
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[BL31_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl31_uuid_spec,
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open_fip
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},
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[BL32_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_uuid_spec,
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open_fip
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},
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[BL33_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl33_uuid_spec,
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open_fip
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},
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[TB_FW_CONFIG_ID] = {
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&fip_dev_handle,
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(uintptr_t)&tb_fw_config_uuid_spec,
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open_fip
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},
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[HW_CONFIG_ID] = {
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&fip_dev_handle,
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(uintptr_t)&hw_config_uuid_spec,
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open_fip
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},
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#if TRUSTED_BOARD_BOOT
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[TRUSTED_BOOT_FW_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&tb_fw_cert_uuid_spec,
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open_fip
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},
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[TRUSTED_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&trusted_key_cert_uuid_spec,
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open_fip
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},
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[SCP_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&fuse_key_cert_uuid_spec,
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open_fip
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},
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[SOC_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&soc_fw_key_cert_uuid_spec,
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open_fip
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},
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[TRUSTED_OS_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&tos_fw_key_cert_uuid_spec,
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open_fip
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},
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[NON_TRUSTED_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&nt_fw_key_cert_uuid_spec,
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open_fip
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},
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[SCP_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&fuse_cert_uuid_spec,
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open_fip
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},
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[SOC_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&soc_fw_cert_uuid_spec,
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open_fip
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},
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[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&tos_fw_cert_uuid_spec,
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open_fip
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},
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[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&nt_fw_cert_uuid_spec,
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open_fip
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},
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#endif /* TRUSTED_BOARD_BOOT */
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};
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak plat_io_setup
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/*
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* Return an IO device handle and specification which can be used to access
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*/
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static int open_fip(const uintptr_t spec)
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{
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int result;
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uintptr_t local_image_handle;
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/* See if a Firmware Image Package is available */
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result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
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if (result == 0) {
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result = io_open(fip_dev_handle, spec, &local_image_handle);
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if (result == 0) {
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VERBOSE("Using FIP\n");
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io_close(local_image_handle);
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}
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}
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return result;
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}
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int open_backend(const uintptr_t spec)
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{
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int result;
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uintptr_t local_image_handle;
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result = io_dev_init(backend_dev_handle, (uintptr_t)NULL);
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if (result == 0) {
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result = io_open(backend_dev_handle, spec, &local_image_handle);
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if (result == 0) {
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io_close(local_image_handle);
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}
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}
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return result;
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}
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#if defined(SD_BOOT) || defined(EMMC_BOOT) || defined(NAND_BOOT)
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static int plat_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec)
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{
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int io_result;
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fip_block_spec.offset = fip_offset;
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io_result = register_io_dev_block(&backend_dev_con);
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assert(io_result == 0);
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/* Open connections to devices and cache the handles */
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io_result = io_dev_open(backend_dev_con, block_dev_spec,
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&backend_dev_handle);
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assert(io_result == 0);
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return io_result;
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}
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#endif
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#if defined(FLEXSPI_NOR_BOOT) || defined(QSPI_BOOT) || defined(NOR_BOOT)
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static int plat_io_memmap_setup(size_t fip_offset)
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{
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int io_result;
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fip_block_spec.offset = fip_offset;
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io_result = register_io_dev_memmap(&backend_dev_con);
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assert(io_result == 0);
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/* Open connections to devices and cache the handles */
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io_result = io_dev_open(backend_dev_con, (uintptr_t)NULL,
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&backend_dev_handle);
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assert(io_result == 0);
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return io_result;
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}
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#endif
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static int ls_io_fip_setup(unsigned int boot_dev)
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{
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int io_result;
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io_result = register_io_dev_fip(&fip_dev_con);
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assert(io_result == 0);
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/* Open connections to devices and cache the handles */
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io_result = io_dev_open(fip_dev_con, (uintptr_t)&fip_device,
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&fip_dev_handle);
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assert(io_result == 0);
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#ifdef CONFIG_DDR_FIP_IMAGE
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/* Open connection to DDR FIP image if available */
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io_result = ddr_fip_setup(fip_dev_con, boot_dev);
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assert(io_result == 0);
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#endif
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#ifdef POLICY_FUSE_PROVISION
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/* Open connection to FUSE FIP image if available */
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io_result = fuse_fip_setup(fip_dev_con, boot_dev);
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assert(io_result == 0);
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#endif
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return io_result;
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}
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int ls_qspi_io_setup(void)
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{
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#ifdef QSPI_BOOT
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qspi_io_setup(NXP_QSPI_FLASH_ADDR,
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NXP_QSPI_FLASH_SIZE,
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PLAT_FIP_OFFSET);
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return plat_io_memmap_setup(NXP_QSPI_FLASH_ADDR + PLAT_FIP_OFFSET);
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#else
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ERROR("QSPI driver not present. Check your BUILD\n");
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/* Should never reach here */
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assert(false);
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return -1;
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#endif
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}
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int emmc_sdhc2_io_setup(void)
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{
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#if defined(EMMC_BOOT) && defined(NXP_ESDHC2_ADDR)
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uintptr_t block_dev_spec;
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int ret;
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ret = sd_emmc_init(&block_dev_spec,
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NXP_ESDHC2_ADDR,
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NXP_SD_BLOCK_BUF_ADDR,
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NXP_SD_BLOCK_BUF_SIZE,
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false);
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if (ret != 0) {
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return ret;
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}
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return plat_io_block_setup(PLAT_FIP_OFFSET, block_dev_spec);
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#else
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ERROR("EMMC driver not present. Check your BUILD\n");
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/* Should never reach here */
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assert(false);
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return -1;
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#endif
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}
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int emmc_io_setup(void)
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{
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/* On the platforms which only has one ESDHC controller,
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* eMMC-boot will use the first ESDHC controller.
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*/
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#if defined(SD_BOOT) || defined(EMMC_BOOT)
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uintptr_t block_dev_spec;
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int ret;
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ret = sd_emmc_init(&block_dev_spec,
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NXP_ESDHC_ADDR,
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NXP_SD_BLOCK_BUF_ADDR,
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NXP_SD_BLOCK_BUF_SIZE,
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true);
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if (ret != 0) {
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return ret;
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}
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return plat_io_block_setup(PLAT_FIP_OFFSET, block_dev_spec);
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#else
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ERROR("SD driver not present. Check your BUILD\n");
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/* Should never reach here */
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assert(false);
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return -1;
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#endif
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}
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int ifc_nor_io_setup(void)
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{
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#if defined(NOR_BOOT)
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int ret;
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ret = ifc_nor_init(NXP_NOR_FLASH_ADDR,
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NXP_NOR_FLASH_SIZE);
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if (ret != 0) {
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return ret;
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}
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return plat_io_memmap_setup(NXP_NOR_FLASH_ADDR + PLAT_FIP_OFFSET);
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#else
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ERROR("NOR driver not present. Check your BUILD\n");
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/* Should never reach here */
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assert(false);
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return -1;
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#endif
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}
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int ifc_nand_io_setup(void)
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{
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#if defined(NAND_BOOT)
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uintptr_t block_dev_spec;
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int ret;
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ret = ifc_nand_init(&block_dev_spec,
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NXP_IFC_REGION_ADDR,
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NXP_IFC_ADDR,
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NXP_IFC_SRAM_BUFFER_SIZE,
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NXP_SD_BLOCK_BUF_ADDR,
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NXP_SD_BLOCK_BUF_SIZE);
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if (ret != 0) {
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return ret;
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}
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return plat_io_block_setup(PLAT_FIP_OFFSET, block_dev_spec);
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#else
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ERROR("NAND driver not present. Check your BUILD\n");
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/* Should never reach here */
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assert(false);
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return -1;
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#endif
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}
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int ls_flexspi_nor_io_setup(void)
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{
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#ifdef FLEXSPI_NOR_BOOT
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int ret = 0;
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ret = flexspi_nor_io_setup(NXP_FLEXSPI_FLASH_ADDR,
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NXP_FLEXSPI_FLASH_SIZE,
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NXP_FLEXSPI_ADDR);
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if (ret != 0) {
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ERROR("FlexSPI NOR driver initialization error.\n");
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/* Should never reach here */
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assert(0);
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panic();
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return -1;
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}
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return plat_io_memmap_setup(NXP_FLEXSPI_FLASH_ADDR + PLAT_FIP_OFFSET);
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#else
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ERROR("FlexSPI NOR driver not present. Check your BUILD\n");
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/* Should never reach here */
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assert(false);
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return -1;
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#endif
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}
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static int (* const ls_io_setup_table[])(void) = {
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[BOOT_DEVICE_IFC_NOR] = ifc_nor_io_setup,
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[BOOT_DEVICE_IFC_NAND] = ifc_nand_io_setup,
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[BOOT_DEVICE_QSPI] = ls_qspi_io_setup,
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[BOOT_DEVICE_EMMC] = emmc_io_setup,
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[BOOT_DEVICE_SDHC2_EMMC] = emmc_sdhc2_io_setup,
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[BOOT_DEVICE_FLEXSPI_NOR] = ls_flexspi_nor_io_setup,
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[BOOT_DEVICE_FLEXSPI_NAND] = ls_flexspi_nor_io_setup,
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};
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int plat_io_setup(void)
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{
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int (*io_setup)(void);
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unsigned int boot_dev = BOOT_DEVICE_NONE;
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int ret;
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boot_dev = get_boot_dev();
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if (boot_dev == BOOT_DEVICE_NONE) {
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ERROR("Boot Device detection failed, Check RCW_SRC\n");
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return -EINVAL;
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}
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io_setup = ls_io_setup_table[boot_dev];
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ret = io_setup();
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if (ret != 0) {
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return ret;
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}
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ret = ls_io_fip_setup(boot_dev);
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if (ret != 0) {
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return ret;
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}
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return 0;
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}
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/* Return an IO device handle and specification which can be used to access
|
|
* an image. Use this to enforce platform load policy
|
|
*/
|
|
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
|
|
uintptr_t *image_spec)
|
|
{
|
|
int result = -1;
|
|
const struct plat_io_policy *policy;
|
|
|
|
if (image_id < ARRAY_SIZE(policies)) {
|
|
|
|
policy = &policies[image_id];
|
|
result = policy->check(policy->image_spec);
|
|
if (result == 0) {
|
|
*image_spec = policy->image_spec;
|
|
*dev_handle = *(policy->dev_handle);
|
|
}
|
|
}
|
|
#ifdef CONFIG_DDR_FIP_IMAGE
|
|
else {
|
|
VERBOSE("Trying alternative IO\n");
|
|
result = plat_get_ddr_fip_image_source(image_id, dev_handle,
|
|
image_spec, open_backend);
|
|
}
|
|
#endif
|
|
#ifdef POLICY_FUSE_PROVISION
|
|
if (result != 0) {
|
|
VERBOSE("Trying FUSE IO\n");
|
|
result = plat_get_fuse_image_source(image_id, dev_handle,
|
|
image_spec, open_backend);
|
|
}
|
|
#endif
|
|
|
|
return result;
|
|
}
|