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https://github.com/ARM-software/arm-trusted-firmware.git
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3ccd7e45a2
Increate SoC name length as it is not enough for some SoC personalities. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I2142b4b5162dd3c9ab3afefcdc859063836d8bcc
152 lines
3.9 KiB
C
152 lines
3.9 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_COMMON_H
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#define PLAT_COMMON_H
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#include <stdbool.h>
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#include <dcfg.h>
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#include <lib/el3_runtime/cpu_data.h>
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#include <platform_def.h>
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#ifdef IMAGE_BL31
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#define BL31_END (uintptr_t)(&__BL31_END__)
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/*******************************************************************************
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* This structure represents the superset of information that can be passed to
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* BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
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* populated only if BL2 detects its presence. A pointer to a structure of this
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* type should be passed in X0 to BL31's cold boot entrypoint.
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*
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* Use of this structure and the X0 parameter is not mandatory: the BL31
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* platform code can use other mechanisms to provide the necessary information
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* about BL32 and BL33 to the common and SPD code.
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*
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* BL31 image information is mandatory if this structure is used. If either of
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* the optional BL32 and BL33 image information is not provided, this is
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* indicated by the respective image_info pointers being zero.
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******************************************************************************/
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typedef struct bl31_params {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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} bl31_params_t;
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/* BL3 utility functions */
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void ls_bl31_early_platform_setup(void *from_bl2,
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void *plat_params_from_bl2);
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/* LS Helper functions */
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unsigned int plat_my_core_mask(void);
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unsigned int plat_core_mask(u_register_t mpidr);
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unsigned int plat_core_pos(u_register_t mpidr);
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//unsigned int plat_my_core_pos(void);
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/* BL31 Data API(s) */
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void _init_global_data(void);
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void _initialize_psci(void);
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uint32_t _getCoreState(u_register_t core_mask);
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void _setCoreState(u_register_t core_mask, u_register_t core_state);
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/* SoC defined structure and API(s) */
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void soc_runtime_setup(void);
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void soc_init(void);
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void soc_platform_setup(void);
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void soc_early_platform_setup2(void);
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#endif /* IMAGE_BL31 */
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#ifdef IMAGE_BL2
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void soc_early_init(void);
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void soc_mem_access(void);
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void soc_preload_setup(void);
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void soc_bl2_prepare_exit(void);
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/* IO storage utility functions */
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int plat_io_setup(void);
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int open_backend(const uintptr_t spec);
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void ls_bl2_plat_arch_setup(void);
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void ls_bl2_el3_plat_arch_setup(void);
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enum boot_device {
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BOOT_DEVICE_IFC_NOR,
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BOOT_DEVICE_IFC_NAND,
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BOOT_DEVICE_QSPI,
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BOOT_DEVICE_EMMC,
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BOOT_DEVICE_SDHC2_EMMC,
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BOOT_DEVICE_FLEXSPI_NOR,
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BOOT_DEVICE_FLEXSPI_NAND,
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BOOT_DEVICE_NONE
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};
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enum boot_device get_boot_dev(void);
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/* DDR Related functions */
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#if DDR_INIT
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#ifdef NXP_WARM_BOOT
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long long init_ddr(uint32_t wrm_bt_flg);
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#else
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long long init_ddr(void);
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#endif
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#endif
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/* Board specific weak functions */
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bool board_enable_povdd(void);
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bool board_disable_povdd(void);
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void mmap_add_ddr_region_dynamically(void);
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#endif /* IMAGE_BL2 */
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typedef struct {
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uint64_t addr;
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uint64_t size;
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} region_info_t;
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typedef struct {
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uint64_t num_dram_regions;
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int64_t total_dram_size;
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region_info_t region[NUM_DRAM_REGIONS];
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} dram_regions_info_t;
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dram_regions_info_t *get_dram_regions_info(void);
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void ls_setup_page_tables(uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit
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#if USE_COHERENT_MEM
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, uintptr_t coh_start,
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uintptr_t coh_limit
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#endif
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);
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#define SOC_NAME_MAX_LEN (20)
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/* Structure to define SoC personality */
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struct soc_type {
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char name[SOC_NAME_MAX_LEN];
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uint32_t version;
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uint8_t num_clusters;
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uint8_t cores_per_cluster;
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};
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void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count,
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uint8_t *num_clusters, uint8_t *cores_per_cluster);
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#define SOC_ENTRY(n, v, ncl, nc) { \
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.name = #n, \
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.version = SVR_##v, \
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.num_clusters = (ncl), \
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.cores_per_cluster = (nc)}
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#endif /* PLAT_COMMON_H */
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