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b53c2c5f2d
For NXP platforms: - Setup files for BL2 and BL31 - Other supporting files. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I36a1183a0652701bdede9e02d41eb976accbb017
61 lines
2 KiB
C
61 lines
2 KiB
C
/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef BL31_DATA_H
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#define BL31_DATA_H
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#define SECURE_DATA_BASE NXP_OCRAM_ADDR
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#define SECURE_DATA_SIZE NXP_OCRAM_SIZE
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#define SECURE_DATA_TOP (SECURE_DATA_BASE + SECURE_DATA_SIZE)
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#define SMC_REGION_SIZE 0x80
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#define SMC_GLBL_BASE (SECURE_DATA_TOP - SMC_REGION_SIZE)
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#define BC_PSCI_DATA_SIZE 0xC0
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#define BC_PSCI_BASE (SMC_GLBL_BASE - BC_PSCI_DATA_SIZE)
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#define SECONDARY_TOP BC_PSCI_BASE
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#define SEC_PSCI_DATA_SIZE 0xC0
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#define SEC_REGION_SIZE SEC_PSCI_DATA_SIZE
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/* SMC global data */
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#define BOOTLOC_OFFSET 0x0
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#define BOOT_SVCS_OSET 0x8
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/* offset to prefetch disable mask */
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#define PREFETCH_DIS_OFFSET 0x10
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/* must reference last smc global entry */
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#define LAST_SMC_GLBL_OFFSET 0x18
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#define SMC_TASK_OFFSET 0xC
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#define TSK_START_OFFSET 0x0
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#define TSK_DONE_OFFSET 0x4
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#define TSK_CORE_OFFSET 0x8
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#define SMC_TASK1_BASE (SMC_GLBL_BASE + 32)
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#define SMC_TASK2_BASE (SMC_TASK1_BASE + SMC_TASK_OFFSET)
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#define SMC_TASK3_BASE (SMC_TASK2_BASE + SMC_TASK_OFFSET)
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#define SMC_TASK4_BASE (SMC_TASK3_BASE + SMC_TASK_OFFSET)
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/* psci data area offsets */
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#define CORE_STATE_DATA 0x0
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#define SPSR_EL3_DATA 0x8
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#define CNTXT_ID_DATA 0x10
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#define START_ADDR_DATA 0x18
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#define LINK_REG_DATA 0x20
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#define GICC_CTLR_DATA 0x28
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#define ABORT_FLAG_DATA 0x30
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#define SCTLR_DATA 0x38
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#define CPUECTLR_DATA 0x40
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#define AUX_01_DATA 0x48 /* usage defined per SoC */
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#define AUX_02_DATA 0x50 /* usage defined per SoC */
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#define AUX_03_DATA 0x58 /* usage defined per SoC */
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#define AUX_04_DATA 0x60 /* usage defined per SoC */
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#define AUX_05_DATA 0x68 /* usage defined per SoC */
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#define AUX_06_DATA 0x70 /* usage defined per SoC */
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#define AUX_07_DATA 0x78 /* usage defined per SoC */
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#define SCR_EL3_DATA 0x80
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#define HCR_EL2_DATA 0x88
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#endif /* BL31_DATA_H */
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