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3a2cc2e262
Define CPUECTLR_TIMER_2TICKS. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Iecb5ede82939e8502d2f1bc74ec3bfe2a00be65c
145 lines
3.8 KiB
C
145 lines
3.8 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_PSCI_H
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#define PLAT_PSCI_H
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#include <cortex_a53.h>
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#include <cortex_a72.h>
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/* core abort current op */
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#define CORE_ABORT_OP 0x1
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/* psci power levels - these are actually affinity levels
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* in the psci_power_state_t array
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*/
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#define PLAT_CORE_LVL PSCI_CPU_PWR_LVL
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#define PLAT_CLSTR_LVL U(1)
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#define PLAT_SYS_LVL U(2)
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#define PLAT_MAX_LVL PLAT_SYS_LVL
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/* core state */
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/* OFF states 0x0 - 0xF */
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#define CORE_IN_RESET 0x0
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#define CORE_DISABLED 0x1
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#define CORE_OFF 0x2
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#define CORE_STANDBY 0x3
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#define CORE_PWR_DOWN 0x4
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#define CORE_WFE 0x6
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#define CORE_WFI 0x7
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#define CORE_LAST 0x8
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#define CORE_OFF_PENDING 0x9
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#define CORE_WORKING_INIT 0xA
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#define SYS_OFF_PENDING 0xB
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#define SYS_OFF 0xC
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/* ON states 0x10 - 0x1F */
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#define CORE_PENDING 0x10
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#define CORE_RELEASED 0x11
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#define CORE_WAKEUP 0x12
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/* highest off state */
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#define CORE_OFF_MAX 0xF
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/* lowest on state */
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#define CORE_ON_MIN CORE_PENDING
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#define DAIF_SET_MASK 0x3C0
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#define SCTLR_I_C_M_MASK 0x00001005
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#define SCTLR_C_MASK 0x00000004
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#define SCTLR_I_MASK 0x00001000
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#define CPUACTLR_L1PCTL_MASK 0x0000E000
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#define DCSR_RCPM2_BASE 0x20170000
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#define CPUECTLR_SMPEN_MASK 0x40
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#define CPUECTLR_SMPEN_EN 0x40
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#define CPUECTLR_RET_MASK 0x7
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#define CPUECTLR_RET_SET 0x2
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#define CPUECTLR_TIMER_MASK 0x7
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#define CPUECTLR_TIMER_8TICKS 0x2
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#define CPUECTLR_TIMER_2TICKS 0x1
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#define SCR_IRQ_MASK 0x2
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#define SCR_FIQ_MASK 0x4
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/* pwr mgmt features supported in the soc-specific code:
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* value == 0x0, the soc code does not support this feature
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* value != 0x0, the soc code supports this feature
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*/
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#ifndef SOC_CORE_RELEASE
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#define SOC_CORE_RELEASE 0x1
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#endif
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#ifndef SOC_CORE_RESTART
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#define SOC_CORE_RESTART 0x1
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#endif
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#ifndef SOC_CORE_OFF
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#define SOC_CORE_OFF 0x1
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#endif
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#ifndef SOC_CORE_STANDBY
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#define SOC_CORE_STANDBY 0x1
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#endif
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#ifndef SOC_CORE_PWR_DWN
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#define SOC_CORE_PWR_DWN 0x1
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#endif
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#ifndef SOC_CLUSTER_STANDBY
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#define SOC_CLUSTER_STANDBY 0x1
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#endif
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#ifndef SOC_CLUSTER_PWR_DWN
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#define SOC_CLUSTER_PWR_DWN 0x1
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#endif
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#ifndef SOC_SYSTEM_STANDBY
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#define SOC_SYSTEM_STANDBY 0x1
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#endif
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#ifndef SOC_SYSTEM_PWR_DWN
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#define SOC_SYSTEM_PWR_DWN 0x1
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#endif
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#ifndef SOC_SYSTEM_OFF
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#define SOC_SYSTEM_OFF 0x1
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#endif
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#ifndef SOC_SYSTEM_RESET
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#define SOC_SYSTEM_RESET 0x1
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#endif
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#ifndef SOC_SYSTEM_RESET2
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#define SOC_SYSTEM_RESET2 0x1
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#endif
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#ifndef __ASSEMBLER__
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void __dead2 _psci_system_reset(void);
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void __dead2 _psci_system_off(void);
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int _psci_cpu_on(u_register_t core_mask);
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void _psci_cpu_prep_off(u_register_t core_mask);
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void __dead2 _psci_cpu_off_wfi(u_register_t core_mask,
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u_register_t wakeup_address);
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void __dead2 _psci_cpu_pwrdn_wfi(u_register_t core_mask,
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u_register_t wakeup_address);
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void __dead2 _psci_sys_pwrdn_wfi(u_register_t core_mask,
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u_register_t wakeup_address);
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void _psci_wakeup(u_register_t core_mask);
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void _psci_core_entr_stdby(u_register_t core_mask);
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void _psci_core_prep_stdby(u_register_t core_mask);
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void _psci_core_exit_stdby(u_register_t core_mask);
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void _psci_core_prep_pwrdn(u_register_t core_mask);
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void _psci_core_exit_pwrdn(u_register_t core_mask);
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void _psci_clstr_prep_stdby(u_register_t core_mask);
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void _psci_clstr_exit_stdby(u_register_t core_mask);
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void _psci_clstr_prep_pwrdn(u_register_t core_mask);
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void _psci_clstr_exit_pwrdn(u_register_t core_mask);
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void _psci_sys_prep_stdby(u_register_t core_mask);
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void _psci_sys_exit_stdby(u_register_t core_mask);
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void _psci_sys_prep_pwrdn(u_register_t core_mask);
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void _psci_sys_exit_pwrdn(u_register_t core_mask);
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#endif
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#endif /* __PLAT_PSCI_H__ */
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