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https://github.com/ARM-software/arm-trusted-firmware.git
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42e35d2f8c
Currently the EL1 part of the context structure (el1_sysregs_t), is coupled with feature flags reducing the context memory allocation for platforms, that don't enable/support all the architectural features at once. Similar to the el2 context optimization commit-"d6af234" this patch further improves this section by converting the assembly context-offset entries into a c structure. It relies on garbage collection of the linker removing unreferenced structures from memory, as well as aiding in readability and future maintenance. Additionally, it eliminates the #ifs usage in 'context_mgmt.c' source file. Change-Id: If6075931cec994bc89231241337eccc7042c5ede Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
149 lines
4.6 KiB
C
149 lines
4.6 KiB
C
/*
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* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <bl31/interrupt_mgmt.h>
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#include <bl31/ehf.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <denver.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#if ENABLE_WDT_LEGACY_FIQ_HANDLING
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#include <flowctrl.h>
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#endif
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#include <tegra_def.h>
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#include <tegra_private.h>
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/* Legacy FIQ used by earlier Tegra platforms */
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#define LEGACY_FIQ_PPI_WDT 28U
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/*******************************************************************************
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* Static variables
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******************************************************************************/
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static uint64_t ns_fiq_handler_addr;
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static uint32_t fiq_handler_active;
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static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* Handler for FIQ interrupts
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******************************************************************************/
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static int tegra_fiq_interrupt_handler(unsigned int id, unsigned int flags,
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void *handle, void *cookie)
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{
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
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uint32_t cpu = plat_my_core_pos();
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(void)flags;
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(void)handle;
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(void)cookie;
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/*
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* Jump to NS world only if the NS world's FIQ handler has
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* been registered
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*/
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if (ns_fiq_handler_addr != 0U) {
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/*
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* The FIQ was generated when the execution was in the non-secure
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* world. Save the context registers to start with.
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*/
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cm_el1_sysregs_context_save(NON_SECURE);
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/*
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* Save elr_el3 and spsr_el3 from the saved context, and overwrite
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* the context with the NS fiq_handler_addr and SPSR value.
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*/
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fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3));
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fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3));
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/*
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* Set the new ELR to continue execution in the NS world using the
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* FIQ handler registered earlier.
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*/
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cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr);
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}
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#if ENABLE_WDT_LEGACY_FIQ_HANDLING
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/*
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* Tegra platforms that use LEGACY_FIQ as the watchdog timer FIQ
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* need to issue an IPI to other CPUs, to allow them to handle
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* the "system hung" scenario. This interrupt is passed to the GICD
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* via the Flow Controller. So, once we receive this interrupt,
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* disable the routing so that we can mark it as "complete" in the
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* GIC later.
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*/
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if (id == LEGACY_FIQ_PPI_WDT) {
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tegra_fc_disable_fiq_to_ccplex_routing();
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}
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#endif
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/*
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* Mark this interrupt as complete to avoid a FIQ storm.
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*/
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plat_ic_end_of_interrupt(id);
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return 0;
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}
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/*******************************************************************************
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* Setup handler for FIQ interrupts
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******************************************************************************/
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void tegra_fiq_handler_setup(void)
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{
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/* return if already registered */
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if (fiq_handler_active == 0U) {
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/*
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* Register an interrupt handler for FIQ interrupts generated for
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* NS interrupt sources
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*/
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ehf_register_priority_handler(PLAT_TEGRA_WDT_PRIO, tegra_fiq_interrupt_handler);
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/* handler is now active */
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fiq_handler_active = 1;
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}
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}
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/*******************************************************************************
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* Validate and store NS world's entrypoint for FIQ interrupts
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******************************************************************************/
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void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint)
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{
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ns_fiq_handler_addr = entrypoint;
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}
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/*******************************************************************************
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* Handler to return the NS EL1/EL0 CPU context
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******************************************************************************/
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int32_t tegra_fiq_get_intr_context(void)
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{
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx);
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const el1_sysregs_t *el1state_ctx = get_el1_sysregs_ctx(ctx);
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uint32_t cpu = plat_my_core_pos();
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uint64_t val;
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/*
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* We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so
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* that el3_exit() sends these values back to the NS world.
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*/
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3));
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3));
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val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0));
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val));
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val = read_el1_ctx_common(el1state_ctx, sp_el1);
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val));
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return 0;
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}
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