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923c221b6d
The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical, decrementing timer as the source. The current logic incorrectly marks this as an incrementing timer, by negating the timer value. This patch fixes the anomaly and updates the driver to remove this logic. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <plat/common/platform.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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static uint32_t tegra_timer_get_value(void)
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{
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/* enable cntps_tval_el1 timer, mask interrupt */
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write_cntps_ctl_el1(CNTP_CTL_IMASK_BIT | CNTP_CTL_ENABLE_BIT);
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/*
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* Generic delay timer implementation expects the timer to be a down
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* counter. The value is clipped from 64 to 32 bits.
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*/
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return (uint32_t)(read_cntps_tval_el1());
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}
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/*
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* Initialise the architecture provided counter as the delay timer.
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*/
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void tegra_delay_timer_init(void)
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{
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static timer_ops_t tegra_timer_ops;
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/* Value in ticks */
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uint32_t multiplier = MHZ_TICKS_PER_SEC;
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/* Value in ticks per second (Hz) */
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uint32_t divider = plat_get_syscnt_freq2();
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/* Reduce multiplier and divider by dividing them repeatedly by 10 */
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while (((multiplier % 10U) == 0U) && ((divider % 10U) == 0U)) {
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multiplier /= 10U;
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divider /= 10U;
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}
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/* enable cntps_tval_el1 timer, mask interrupt */
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write_cntps_ctl_el1(CNTP_CTL_IMASK_BIT | CNTP_CTL_ENABLE_BIT);
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/* register the timer */
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tegra_timer_ops.get_timer_value = tegra_timer_get_value;
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tegra_timer_ops.clk_mult = multiplier;
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tegra_timer_ops.clk_div = divider;
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timer_init(&tegra_timer_ops);
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}
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