mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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edcece15c7
Initial version Signed-off-by: Margarita Glushkin <rutigl@gmail.com> Change-Id: If433d325a90b519ae5f02411865bffd368ff2824
136 lines
3.3 KiB
C
136 lines
3.3 KiB
C
/*
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* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
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*
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* Copyright (C) 2017-2023 Nuvoton Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <npcm845x_clock.h>
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#include <npcm845x_gcr.h>
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#include <npcm845x_lpuart.h>
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#include <plat_npcm845x.h>
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uintptr_t npcm845x_get_base_uart(UART_DEV_T devNum)
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{
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return 0xF0000000 + devNum * 0x1000;
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}
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uintptr_t npcm845x_get_base_clk(void)
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{
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return 0xF0801000;
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}
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uintptr_t npcm845x_get_base_gcr(void)
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{
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return 0xF0800000;
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}
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void npcm845x_wait_for_empty(int uart_n)
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{
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volatile struct npcmX50_uart *uart = (struct npcmX50_uart *)npcm845x_get_base_uart(uart_n);
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while ((*(uint8_t *)(uintptr_t)(&uart->lsr) & 0x40) == 0x00) {
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/*
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* wait for THRE (Transmitter Holding Register Empty)
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* and TSR (Transmitter Shift Register) to be empty.
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* Some delay. notice needed some delay so UartUpdateTool
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* will pass w/o error log
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*/
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}
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volatile int delay;
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for (delay = 0; delay < 10000; delay++) {
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;
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}
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}
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int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate)
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{
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uint32_t val = 0;
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uintptr_t clk_base = npcm845x_get_base_clk();
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uintptr_t gcr_base = npcm845x_get_base_gcr();
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uintptr_t uart_base = npcm845x_get_base_uart(devNum);
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volatile struct npcmX50_uart *uart = (struct npcmX50_uart *)uart_base;
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/* Use CLKREF to be independent of CPU frequency */
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volatile struct clk_ctl *clk_ctl_obj = (struct clk_ctl *)clk_base;
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volatile struct npcm845x_gcr *gcr_ctl_obj =
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(struct npcm845x_gcr *)gcr_base;
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clk_ctl_obj->clksel = clk_ctl_obj->clksel & ~(0x3 << 8);
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clk_ctl_obj->clksel = clk_ctl_obj->clksel | (0x2 << 8);
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/* Set devider according to baudrate */
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clk_ctl_obj->clkdiv1 =
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(unsigned int)(clk_ctl_obj->clkdiv1 & ~(0x1F << 16));
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/* clear bits 11-15 - set value 0 */
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if (devNum == UART3_DEV) {
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clk_ctl_obj->clkdiv2 =
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(unsigned int)(clk_ctl_obj->clkdiv2 & ~(0x1F << 11));
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}
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npcm845x_wait_for_empty(devNum);
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val = (uint32_t)LCR_WLS_8bit;
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mmio_write_8((uintptr_t)&uart->lcr, (uint8_t)val);
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/* disable all interrupts */
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mmio_write_8((uintptr_t)&uart->ier, 0);
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/*
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* Set the RX FIFO trigger level, reset RX, TX FIFO
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*/
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val = (uint32_t)(FCR_FME | FCR_RFR | FCR_TFR | FCR_RFITL_4B);
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/* reset TX and RX FIFO */
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mmio_write_8((uintptr_t)(&uart->fcr), (uint8_t)val);
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/* Set port for 8 bit, 1 stop, no parity */
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val = (uint32_t)LCR_WLS_8bit;
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/* Set DLAB bit; Accesses the Divisor Latch Registers (DLL, DLM). */
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val |= 0x80;
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mmio_write_8((uintptr_t)(&uart->lcr), (uint8_t)val);
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/* Baud Rate = UART Clock 24MHz / (16 * (11+2)) = 115384 */
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mmio_write_8((uintptr_t)(&uart->dll), 11);
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mmio_write_8((uintptr_t)(&uart->dlm), 0x00);
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val = mmio_read_8((uintptr_t)&uart->lcr);
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/* Clear DLAB bit; Accesses RBR, THR or IER registers. */
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val &= 0x7F;
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mmio_write_8((uintptr_t)(&uart->lcr), (uint8_t)val);
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if (devNum == UART0_DEV) {
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gcr_ctl_obj->mfsel4 &= ~(1 << 1);
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gcr_ctl_obj->mfsel1 |= 1 << 9;
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} else if (devNum == UART3_DEV) {
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/* Pin Mux */
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gcr_ctl_obj->mfsel4 &= ~(1 << 1);
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gcr_ctl_obj->mfsel1 |= 1 << 11;
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gcr_ctl_obj->spswc &= (7 << 0);
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gcr_ctl_obj->spswc |= (2 << 0);
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} else {
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/* halt */
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while (1) {
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;
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}
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}
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return 0;
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}
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