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https://github.com/ARM-software/arm-trusted-firmware.git
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ae2b4a5494
gfx frame buffer memory corruption because of moving TF-A to DDR Change-Id: I6f1e0c8d048273b8047497adec631160aaf393d6 Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
214 lines
5.3 KiB
ArmAsm
214 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
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*
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* Copyright (C) 2022-2023 Nuvoton Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NUVOTON_HELPERS_S
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#define NUVOTON_HELPERS_S
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#include <asm_macros.S>
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#include <cortex_a35.h>
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#include <platform_def.h>
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_calc_core_pos
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.globl plat_reset_handler
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl npcm845x_mailbox_init
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/* --------------------------------------------------------------------
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* Helper macro that reads the part number of the current CPU and jumps
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* to the given label if it matches the CPU MIDR provided.
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*
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* Clobbers x0.
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* --------------------------------------------------------------------
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq \_label
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.endm
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/* ----------------------------------------------
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* The mailbox_base is used to distinguish warm/cold
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* reset. The mailbox_base is in the data section, not
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* in .bss, this allows function to start using this
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* variable before the runtime memory is initialized.
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* ----------------------------------------------
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*/
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.section .data.mailbox_base
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.align 3
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mailbox_base: .quad 0x0
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/* ---------------------------------------------
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* void plat_reset_handler(void);
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*
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* To add: Determine the SoC type and call the appropriate
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* reset handler.
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*----------------------------------------------- */
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func plat_reset_handler
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ret
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endfunc plat_reset_handler
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/* ----------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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* This function checks if this is the primary CPU
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* ----------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* ----------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This Function uses the plat_calc_core_pos()
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* to get the index of the calling CPU.
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* ----------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_my_core_pos
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/*
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* unsigned int plat_calc_core_pos(uint64_t mpidr)
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* helper function to calculate the core position.
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* With this function.
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*/
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func plat_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_calc_core_pos
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/* ---------------------------------------------
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* function to get the entrypoint.
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* ---------------------------------------------
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*/
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot.
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*
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* This functions returns:
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* - 0 for a cold boot.
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* - Any other value for a warm boot.
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov x1, x30
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bl plat_is_my_cpu_primary
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/*
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* Secondaries always cold boot.
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*/
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cbz w0, 1f
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/*
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* Primaries warm boot if they are requested
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* to power off.
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*/
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mov_imm x0, PLAT_NPCM_TM_HOLD_BASE
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ldr x0, [x0]
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cmp x0, PLAT_NPCM_TM_HOLD_STATE_BSP_OFF
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adr x0, plat_wait_for_warm_boot
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csel x0, x0, xzr, eq
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ret x1
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1: mov x0, #0
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ret x1
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endfunc plat_get_my_entrypoint
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func npcm845x_mailbox_init
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adrp x1, mailbox_base
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str x0, [x1, :lo12:mailbox_base]
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ret
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endfunc npcm845x_mailbox_init
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func plat_wait_for_warm_boot
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/*
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* Calculate address of our hold entry.
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* As the function will never return, there is no need to save LR.
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*/
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bl plat_my_core_pos
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lsl x0, x0, #3
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mov_imm x2, PLAT_NPCM_TM_HOLD_BASE
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add x0, x0, x2
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mov x8, x0
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mov_imm x2, PLAT_NPCM_TRUSTED_NOTIFICATION_BASE
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add x8, x8, x2
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/*
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* This code runs way before requesting the warmboot of this core,
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* so it is possible to clear the mailbox before getting a request
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* to boot.
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*/
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mov x1, PLAT_NPCM_TM_HOLD_STATE_WAIT
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str x1,[x0]
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/* Notify that core is in pending state - do not use x0!, uses x7 and x8! */
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mov x7, PLAT_NPCM_TM_NOTIFICATION_START
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str x7,[x8]
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/*
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* This code runs way before requesting the warmboot of this core,
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* so it is possible to clear the mailbox before getting a request
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* to boot.
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*/
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mov x1, PLAT_NPCM_TM_HOLD_STATE_WAIT
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str x1,[x0]
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/* Wait until we have a go */
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poll_mailbox:
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wfe
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ldr x1, [x0]
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cmp x1, PLAT_NPCM_TM_HOLD_STATE_GO
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bne poll_mailbox
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mov x7, PLAT_NPCM_TM_NOTIFICATION_BR
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str x7,[x8]
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/* Jump to the provided entrypoint */
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mov_imm x0, PLAT_NPCM_TM_ENTRYPOINT
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ldr x1, [x0]
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br x1
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endfunc plat_wait_for_warm_boot
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func plat_secondary_cold_boot_setup
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b plat_wait_for_warm_boot
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endfunc plat_secondary_cold_boot_setup
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func plat_crash_console_init
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mov x0, #1
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ret
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endfunc plat_crash_console_init
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func plat_crash_console_putc
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ret
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov x0, #0
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ret
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endfunc plat_crash_console_flush
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func platform_mem_init
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ret
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endfunc platform_mem_init
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#endif /* NUVOTON_HELPERS_S */
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