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cc76896d9e
To use cirq drivers more easier, we place mtk_cirq.c and mtk_cirq.h to common/drivers/cirq. We also rename mtk_cirq.c/h to mt_cirq.c/h for consistency with other driver folders. TEST=build pass for mt8192/mt8195/mt8186 BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I71bc442f00b16fb4031260937982c0496fcaaea0
122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
/*
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* Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MT_CIRQ_H
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#define PLAT_MT_CIRQ_H
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#include <stdint.h>
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#include <platform_def.h>
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enum {
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IRQ_MASK_HEADER = 0xF1F1F1F1,
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IRQ_MASK_FOOTER = 0xF2F2F2F2
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};
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struct mtk_irq_mask {
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uint32_t header; /* for error checking */
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uint32_t mask0;
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uint32_t mask1;
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uint32_t mask2;
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uint32_t mask3;
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uint32_t mask4;
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uint32_t mask5;
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uint32_t mask6;
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uint32_t mask7;
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uint32_t mask8;
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uint32_t mask9;
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uint32_t mask10;
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uint32_t mask11;
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uint32_t mask12;
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uint32_t footer; /* for error checking */
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};
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/*
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* Define hardware register
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*/
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#define CIRQ_STA_BASE (SYS_CIRQ_BASE + U(0x000))
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#define CIRQ_ACK_BASE (SYS_CIRQ_BASE + U(0x080))
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#define CIRQ_MASK_BASE (SYS_CIRQ_BASE + U(0x100))
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#define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + U(0x180))
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#define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + U(0x200))
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#define CIRQ_SENS_BASE (SYS_CIRQ_BASE + U(0x280))
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#define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + U(0x300))
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#define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + U(0x380))
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#define CIRQ_POL_BASE (SYS_CIRQ_BASE + U(0x400))
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#define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + U(0x480))
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#define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + U(0x500))
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#define CIRQ_CON (SYS_CIRQ_BASE + U(0x600))
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/*
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* Register placement
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*/
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#define CIRQ_CON_EN_BITS U(0)
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#define CIRQ_CON_EDGE_ONLY_BITS U(1)
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#define CIRQ_CON_FLUSH_BITS U(2)
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#define CIRQ_CON_SW_RST_BITS U(20)
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#define CIRQ_CON_EVENT_BITS U(31)
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#define CIRQ_CON_BITS_MASK U(0x7)
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/*
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* Register setting
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*/
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#define CIRQ_CON_EN U(0x1)
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#define CIRQ_CON_EDGE_ONLY U(0x1)
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#define CIRQ_CON_FLUSH U(0x1)
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#define CIRQ_SW_RESET U(0x1)
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/*
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* Define constant
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*/
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#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U)
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#define MT_CIRQ_POL_NEG U(0)
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#define MT_CIRQ_POL_POS U(1)
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#define IRQ_TO_CIRQ_NUM(irq) ((irq) - (32U + CIRQ_SPI_START))
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#define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (32U + CIRQ_SPI_START))
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/* GIC sensitive */
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#define SENS_EDGE U(0x2)
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#define SENS_LEVEL U(0x1)
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/*
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* Define function prototypes.
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*/
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int mt_cirq_test(void);
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void mt_cirq_dump_reg(void);
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int mt_irq_mask_restore(struct mtk_irq_mask *mask);
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int mt_irq_mask_all(struct mtk_irq_mask *mask);
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void mt_cirq_clone_gic(void);
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void mt_cirq_enable(void);
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void mt_cirq_flush(void);
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void mt_cirq_disable(void);
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void mt_irq_unmask_for_sleep_ex(uint32_t irq);
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void set_wakeup_sources(uint32_t *list, uint32_t num_of_events);
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void mt_cirq_sw_reset(void);
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struct cirq_reg {
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uint32_t reg_num;
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uint32_t used;
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uint32_t mask;
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uint32_t pol;
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uint32_t sen;
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uint32_t pending;
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uint32_t the_link;
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};
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struct cirq_events {
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uint32_t num_reg;
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uint32_t spi_start;
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uint32_t num_of_events;
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uint32_t *wakeup_events;
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struct cirq_reg table[CIRQ_REG_NUM];
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uint32_t dist_base;
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uint32_t cirq_base;
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uint32_t used_reg_head;
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};
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#endif /* PLAT_MT_CIRQ_H */
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