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ce21a1a909
DDR and IOSSM driver code for Agilex5 platform, initialize the DDR/IOSSM in BL2 EL3 early flow. Change-Id: I3e4205171d9356190b60498cae322318520bb1c2 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
155 lines
4.4 KiB
C
155 lines
4.4 KiB
C
/*
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGILEX5_IOSSM_MAILBOX_H
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#define AGILEX5_IOSSM_MAILBOX_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "lib/mmio.h"
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#include "agilex5_ddr.h"
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#define TIMEOUT_5000MS 5000
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#define TIMEOUT TIMEOUT_5000MS
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#define IOSSM_STATUS_CAL_SUCCESS BIT(0)
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#define IOSSM_STATUS_CAL_FAIL BIT(1)
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#define IOSSM_STATUS_CAL_BUSY BIT(2)
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#define IOSSM_STATUS_COMMAND_RESPONSE_READY 1
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#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C
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#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458
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#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454
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#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450
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#define IOSSM_CMD_REQ_OFFSET 0x43C
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#define IOSSM_CMD_PARAM_0_OFFSET 0x438
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#define IOSSM_CMD_PARAM_1_OFFSET 0x434
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#define IOSSM_CMD_PARAM_2_OFFSET 0x430
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#define IOSSM_CMD_PARAM_3_OFFSET 0x42C
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#define IOSSM_CMD_PARAM_4_OFFSET 0x428
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#define IOSSM_CMD_PARAM_5_OFFSET 0x424
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#define IOSSM_CMD_PARAM_6_OFFSET 0x420
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#define IOSSM_STATUS_OFFSET 0x400
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#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16)
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#define IOSSM_CMD_RESPONSE_DATA_SHORT(data) (((data) & \
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IOSSM_CMD_RESPONSE_DATA_SHORT_MASK) >> 16)
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#define MAX_IO96B_SUPPORTED 2
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#define MAX_MEM_INTERFACES_SUPPORTED 2
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/* supported mailbox command type */
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enum iossm_mailbox_cmd_type {
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CMD_NOP,
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CMD_GET_SYS_INFO,
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CMD_GET_MEM_INFO,
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CMD_GET_MEM_CAL_INFO,
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CMD_TRIG_CONTROLLER_OP,
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CMD_TRIG_MEM_CAL_OP
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};
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/* supported mailbox command opcode */
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enum iossm_mailbox_cmd_opcode {
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GET_MEM_INTF_INFO = 0x0001,
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GET_MEM_TECHNOLOGY,
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GET_MEMCLK_FREQ_KHZ,
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GET_MEM_WIDTH_INFO,
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ECC_ENABLE_SET = 0x0101,
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ECC_ENABLE_STATUS,
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ECC_INTERRUPT_STATUS,
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ECC_INTERRUPT_ACK,
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ECC_INTERRUPT_MASK,
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ECC_WRITEBACK_ENABLE,
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ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201,
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ECC_SCRUB_MODE_0_START,
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ECC_SCRUB_MODE_1_START,
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BIST_STANDARD_MODE_START = 0x0301,
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BIST_RESULTS_STATUS,
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BIST_MEM_INIT_START,
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BIST_MEM_INIT_STATUS,
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BIST_SET_DATA_PATTERN_UPPER,
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BIST_SET_DATA_PATTERN_LOWER,
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TRIG_MEM_CAL = 0x000a,
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GET_MEM_CAL_STATUS
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};
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/*
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* IOSSM mailbox required information
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*
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* @num_mem_interface: Number of memory interfaces instantiated
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* @ip_type: IP type implemented on the IO96B
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* @ip_instance_id: IP identifier for every IP instance implemented on the IO96B
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*/
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struct io96b_mb_ctrl {
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uint32_t num_mem_interface;
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uint32_t ip_type[2];
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uint32_t ip_instance_id[2];
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};
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/*
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* IOSSM mailbox response outputs
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*
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* @cmd_resp_status: Command Interface status
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* @cmd_resp_data_*: More spaces for command response
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*/
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struct io96b_mb_resp {
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uint32_t cmd_resp_status;
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uint32_t cmd_resp_data_0;
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uint32_t cmd_resp_data_1;
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uint32_t cmd_resp_data_2;
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};
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/*
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* IO96B instance specific information
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*
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* @size: Memory size
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* @io96b_csr_addr: IO96B instance CSR address
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* @cal_status: IO96B instance calibration status
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* @mb_ctrl: IOSSM mailbox required information
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*/
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struct io96b_instance {
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uint16_t size;
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phys_addr_t io96b_csr_addr;
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bool cal_status;
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struct io96b_mb_ctrl mb_ctrl;
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};
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/*
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* Overall IO96B instance(s) information
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*
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* @num_instance: Number of instance(s) assigned to HPS
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* @overall_cal_status: Overall calibration status for all IO96B instance(s)
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* @ddr_type: DDR memory type
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* @ecc_status: ECC enable status (false = disabled, true = enabled)
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* @overall_size: Total DDR memory size
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* @io96b_0: IO96B 0 instance specific information
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* @io96b_1: IO96B 1 instance specific information
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*/
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struct io96b_info {
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uint8_t num_instance;
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bool overall_cal_status;
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const char *ddr_type;
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bool ecc_status;
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uint16_t overall_size;
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struct io96b_instance io96b_0;
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struct io96b_instance io96b_1;
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};
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int io96b_mb_req(phys_addr_t io96b_csr_addr, uint32_t ip_type, uint32_t instance_id,
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uint32_t usr_cmd_type, uint32_t usr_cmd_opcode, uint32_t cmd_param_0,
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uint32_t cmd_param_1, uint32_t cmd_param_2, uint32_t cmd_param_3,
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uint32_t cmd_param_4, uint32_t cmd_param_5, uint32_t cmd_param_6,
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uint32_t resp_data_len, struct io96b_mb_resp *resp);
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/* Supported IOSSM mailbox function */
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void io96b_mb_init(struct io96b_info *io96b_ctrl);
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int io96b_cal_status(phys_addr_t addr);
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void init_mem_cal(struct io96b_info *io96b_ctrl);
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int trig_mem_cal(struct io96b_info *io96b_ctrl);
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int get_mem_technology(struct io96b_info *io96b_ctrl);
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int get_mem_width_info(struct io96b_info *io96b_ctrl);
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int ecc_enable_status(struct io96b_info *io96b_ctrl);
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int bist_mem_init_start(struct io96b_info *io96b_ctrl);
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#endif /* AGILEX5_IOSSM_MAILBOX_H */
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