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ce21a1a909
DDR and IOSSM driver code for Agilex5 platform, initialize the DDR/IOSSM in BL2 EL3 early flow. Change-Id: I3e4205171d9356190b60498cae322318520bb1c2 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
31 lines
581 B
C
31 lines
581 B
C
/*
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGILEX5_DDR_H
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#define AGILEX5_DDR_H
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <lib/utils_def.h>
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#include "socfpga_handoff.h"
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#define CONFIG_NR_DRAM_BANKS 1
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typedef unsigned long long phys_addr_t;
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typedef unsigned long long phys_size_t;
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typedef phys_addr_t fdt_addr_t;
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/* DDR/RAM configuration */
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struct ddr_info {
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phys_addr_t start;
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phys_size_t size;
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};
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int agilex5_ddr_init(handoff *hoff_ptr);
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#endif /* AGILEX5_DDR_H */
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