mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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2368d7b157
Add the basic boot support for i.MX93. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I48bac2fd8bf2145133edf101a315908266c3f50a
216 lines
5.1 KiB
C
216 lines
5.1 KiB
C
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PWR_CTRL_H
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#define PWR_CTRL_H
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#include <stdbool.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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/*******************************************************************************
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* GPC definitions & declarations
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******************************************************************************/
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/* GPC GLOBAL */
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#define GPC_GLOBAL_BASE U(GPC_BASE + 0x4000)
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#define GPC_AUTHEN_CTRL U(0x4)
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#define GPC_DOMAIN U(0x10)
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#define GPC_MASTER U(0x1c)
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#define GPC_SYS_SLEEP U(0x40)
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#define PMIC_CTRL U(0x100)
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#define PMIC_PRE_DLY_CTRL U(0x104)
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#define PMIC_STBY_ACK_CTRL U(0x108)
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#define GPC_ROSC_CTRL U(0x200)
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#define GPC_AON_MEM_CTRL U(0x204)
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#define GPC_EFUSE_CTRL U(0x208)
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#define FORCE_CPUx_DISABLE(x) (1 << (16 + (x)))
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#define PMIC_STBY_EN BIT(0)
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#define ROSC_OFF_EN BIT(0)
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/* GPC CPU_CTRL */
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#define CM_SLICE(x) (GPC_BASE + 0x800 * (x))
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#define CM_AUTHEN_CTRL U(0x4)
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#define CM_MISC U(0xc)
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#define CM_MODE_CTRL U(0x10)
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#define CM_IRQ_WAKEUP_MASK0 U(0x100)
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#define CM_SYS_SLEEP_CTRL U(0x380)
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#define IMR_NUM U(8)
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/* CM_MISC */
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#define SLEEP_HOLD_EN BIT(1)
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#define IRQ_MUX BIT(5)
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#define SW_WAKEUP BIT(6)
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/* CM_SYS_SLEEP_CTRL */
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#define SS_WAIT BIT(0)
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#define SS_STOP BIT(1)
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#define SS_SUSPEND BIT(2)
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#define CM_MODE_RUN U(0x0)
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#define CM_MODE_WAIT U(0x1)
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#define CM_MODE_STOP U(0x2)
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#define CM_MODE_SUSPEND U(0x3)
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#define LPM_SETTING(d, m) ((m) << (((d) % 8) * 4))
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enum gpc_cmc_slice {
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CPU_M33,
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CPU_A55C0,
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CPU_A55C1,
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CPU_A55_PLAT,
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};
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/* set gpc domain assignment */
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static inline void gpc_assign_domains(unsigned int domains)
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{
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mmio_write_32(GPC_GLOBAL_BASE + GPC_DOMAIN, domains);
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}
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/* force a cpu into sleep status */
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static inline void gpc_force_cpu_suspend(unsigned int cpu)
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{
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mmio_setbits_32(GPC_GLOBAL_BASE + GPC_SYS_SLEEP, FORCE_CPUx_DISABLE(cpu));
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}
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static inline void gpc_pmic_stby_en(bool en)
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{
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mmio_write_32(GPC_GLOBAL_BASE + PMIC_CTRL, en ? 1 : 0);
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}
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static inline void gpc_rosc_off(bool off)
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{
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mmio_write_32(GPC_GLOBAL_BASE + GPC_ROSC_CTRL, off ? 1 : 0);
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}
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static inline void gpc_set_cpu_mode(unsigned int cpu, unsigned int mode)
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{
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mmio_write_32(CM_SLICE(cpu) + CM_MODE_CTRL, mode);
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}
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static inline void gpc_select_wakeup_gic(unsigned int cpu)
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{
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mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX);
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}
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static inline void gpc_select_wakeup_raw_irq(unsigned int cpu)
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{
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mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX);
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}
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static inline void gpc_assert_sw_wakeup(unsigned int cpu)
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{
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mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP);
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}
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static inline void gpc_deassert_sw_wakeup(unsigned int cpu)
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{
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mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP);
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}
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static inline void gpc_clear_cpu_sleep_hold(unsigned int cpu)
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{
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mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SLEEP_HOLD_EN);
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}
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static inline void gpc_set_irq_mask(unsigned int cpu, unsigned int idx, uint32_t mask)
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{
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mmio_write_32(CM_SLICE(cpu) + idx * 0x4 + CM_IRQ_WAKEUP_MASK0, mask);
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}
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/*******************************************************************************
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* SRC definitions & declarations
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******************************************************************************/
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#define SRC_SLICE(x) (SRC_BASE + 0x400 * (x))
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#define SRC_AUTHEN_CTRL U(0x4)
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#define SRC_LPM_SETTING0 U(0x10)
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#define SRC_LPM_SETTING1 U(0x14)
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#define SRC_LPM_SETTING2 U(0x18)
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#define SRC_SLICE_SW_CTRL U(0x20)
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#define SRC_MEM_CTRL U(0x4)
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#define MEM_LP_EN BIT(2)
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#define MEM_LP_RETN BIT(1)
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enum mix_mem_mode {
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MEM_OFF,
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MEM_RETN,
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};
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enum src_mix_mem_slice {
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SRC_GLOBAL,
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/* MIX slice */
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SRC_SENTINEL,
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SRC_AON,
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SRC_WKUP,
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SRC_DDR,
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SRC_DPHY,
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SRC_ML,
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SRC_NIC,
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SRC_HSIO,
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SRC_MEDIA,
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SRC_M33P,
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SRC_A55C0,
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SRC_A55C1,
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SRC_A55P,
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/* MEM slice */
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SRC_AON_MEM,
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SRC_WKUP_MEM,
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SRC_DDR_MEM,
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SRC_DPHY_MEM,
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SRC_ML_MEM,
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SRC_NIC_MEM,
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SRC_NIC_OCRAM,
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SRC_HSIO_MEM,
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SRC_MEDIA_MEM,
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SRC_A55P0_MEM,
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SRC_A55P1_MEM,
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SRC_A55_SCU_MEM,
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SRC_A55_L3_MEM,
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};
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static inline void src_authen_config(unsigned int mix, unsigned int wlist,
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unsigned int lpm_en)
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{
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mmio_write_32(SRC_SLICE(mix) + SRC_AUTHEN_CTRL, (wlist << 16) | (lpm_en << 2));
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}
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static inline void src_mix_set_lpm(unsigned int mix, unsigned int did, unsigned int lpm_mode)
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{
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mmio_clrsetbits_32(SRC_SLICE(mix) + SRC_LPM_SETTING1 + (did / 8) * 0x4,
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LPM_SETTING(did, 0x7), LPM_SETTING(did, lpm_mode));
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}
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static inline void src_mem_lpm_en(unsigned int mix, bool retn)
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{
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mmio_setbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | (retn ? MEM_LP_RETN : 0));
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}
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static inline void src_mem_lpm_dis(unsigned int mix)
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{
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mmio_clrbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | MEM_LP_RETN);
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}
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/*******************************************************************************
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* BLK_CTRL_S definitions & declarations
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******************************************************************************/
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#define HW_LP_HANDHSK U(0x110)
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#define HW_LP_HANDHSK2 U(0x114)
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#define CA55_CPUWAIT U(0x118)
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#define CA55_RVBADDR0_L U(0x11c)
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#define CA55_RVBADDR0_H U(0x120)
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/*******************************************************************************
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* Other definitions & declarations
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******************************************************************************/
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void pwr_sys_init(void);
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#endif /* PWR_CTRL_H */
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