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https://github.com/ARM-software/arm-trusted-firmware.git
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f7434fa135
The commitd76f012ea8("refactor(imx8m): replace magic number with enum type") also hardcodes the domain permissions configuration for the UARTs, causing a regression for any board using a boot console different from UART2. Indeed, previously, the RDC_PDAP_UARTn registers were set to the reset value (0xff), meaning all domains were enabled for read and write access. This patch fixes this regression by ensuring that the console always has read/write access enabled for domain 0. Tested on a i.MX8MN BSH SMM S2 PRO board. Fixes:d76f012ea8("refactor(imx8m): replace magic number with enum type") Change-Id: I2670bf485372f32ef45cebb72a7694a9a800f417 Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
/*
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* Copyright (c) 2019, NXP. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <lib/mmio.h>
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#include <imx_rdc.h>
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struct imx_uart {
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int index;
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unsigned int uart_base;
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};
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static const struct imx_uart imx8m_uart_info[] = {
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{ /* UART 1 */
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.index = RDC_PDAP_UART1,
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.uart_base = IMX_UART1_BASE,
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}, { /* UART 2 */
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.index = RDC_PDAP_UART2,
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.uart_base = IMX_UART2_BASE,
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}, { /* UART 3 */
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.index = RDC_PDAP_UART3,
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.uart_base = IMX_UART3_BASE,
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}, { /* UART 4 */
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.index = RDC_PDAP_UART4,
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.uart_base = IMX_UART4_BASE,
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}
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};
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static int imx_rdc_uart_get_pdap_index(unsigned int uart_base)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(imx8m_uart_info); i++) {
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if (imx8m_uart_info[i].uart_base == uart_base) {
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return imx8m_uart_info[i].index;
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}
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}
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return -ENODEV;
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}
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static void imx_rdc_console_access_enable(struct imx_rdc_cfg *rdc_cfg,
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unsigned int console_base)
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{
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struct imx_rdc_cfg *rdc;
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int console_pdap_index;
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console_pdap_index = imx_rdc_uart_get_pdap_index(console_base);
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if (console_pdap_index < 0) {
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return;
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}
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for (rdc = rdc_cfg; rdc->type != RDC_INVALID; rdc++) {
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if (rdc->type != RDC_PDAP || rdc->index != console_pdap_index) {
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continue;
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}
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if (rdc->index == console_pdap_index &&
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rdc->setting.rdc_pdap == (D0R | D0W)) {
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return;
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}
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if (rdc->index == console_pdap_index) {
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rdc->setting.rdc_pdap = D0R | D0W;
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}
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}
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}
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void imx_rdc_init(struct imx_rdc_cfg *rdc_cfg, unsigned int console_base)
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{
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struct imx_rdc_cfg *rdc = rdc_cfg;
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imx_rdc_console_access_enable(rdc, console_base);
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while (rdc->type != RDC_INVALID) {
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switch (rdc->type) {
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case RDC_MDA:
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/* MDA config */
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mmio_write_32(MDAn(rdc->index), rdc->setting.rdc_mda);
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break;
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case RDC_PDAP:
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/* peripheral access permission config */
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mmio_write_32(PDAPn(rdc->index), rdc->setting.rdc_pdap);
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break;
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case RDC_MEM_REGION:
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/* memory region access permission config */
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mmio_write_32(MRSAn(rdc->index), rdc->setting.rdc_mem_region[0]);
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mmio_write_32(MREAn(rdc->index), rdc->setting.rdc_mem_region[1]);
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mmio_write_32(MRCn(rdc->index), rdc->setting.rdc_mem_region[2]);
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break;
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default:
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break;
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}
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rdc++;
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}
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}
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